公开(公告)号：US20230004386A1

公开(公告)日：2023-01-05

申请号：US17892807

申请日：2022-08-22

Applicant: Google LLC

Inventor： Olivier Temam ,  Ravi Narayanaswami ,  Harshit Khaitan ,  Dong Hyuk Woo

IPC: G06F9/30 ,  G06F13/28 ,  G06N3/04 ,  G06N3/063 ,  G06F9/38

Abstract: A computing unit is disclosed, comprising a first memory bank for storing input activations and a second memory bank for storing parameters used in performing computations. The computing unit includes at least one cell comprising at least one multiply accumulate (“MAC”) operator that receives parameters from the second memory bank and performs computations. The computing unit further includes a first traversal unit that provides a control signal to the first memory bank to cause an input activation to be provided to a data bus accessible by the MAC operator. The computing unit performs one or more computations associated with at least one element of a data array, the one or more computations being performed by the MAC operator and comprising, in part, a multiply operation of the input activation received from the data bus and a parameter received from the second memory bank.

公开(公告)号：US11176493B2

公开(公告)日：2021-11-16

申请号：US16397481

申请日：2019-04-29

Applicant: Google LLC

Inventor： Lawrence J. Madar, III ,  Temitayo Fadelu ,  Harshit Khaitan ,  Ravi Narayanaswami

IPC: G06N20/00

Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for virtualizing external memory as local to a machine learning accelerator. One ambient computing system comprises: an ambient machine learning engine; a low-power CPU; and an SRAM that is shared among at least the ambient machine learning engine and the low-power CPU; wherein the ambient machine learning engine comprises virtual address logic to translate from virtual addresses generated by the ambient machine learning engine to physical addresses within the SRAM.

公开(公告)号：US20190205756A1

公开(公告)日：2019-07-04

申请号：US16297091

申请日：2019-03-08

Applicant: Google LLC

Inventor： Olivier Temam ,  Harshit Khaitan ,  Ravi Narayanaswami ,  Dong Hyuk Woo

IPC: G06N3/08 ,  G06N20/00 ,  G06F8/41 ,  G06N3/063

CPC classification number: G06N3/08 ,  G06F8/4441 ,  G06F8/452 ,  G06F9/50 ,  G06N3/04 ,  G06N3/063 ,  G06N20/00 ,  G06T1/20

Abstract: Methods, systems, and apparatus for accessing a N-dimensional tensor are described. In some implementations, a method includes, for each of one or more first iterations of a first nested loop, performing iterations of a second nested loop that is nested within the first nested loop until a first loop bound for the second nested loop is reached. A number of iterations of the second nested loop for the one or more first iterations of the first nested loop is limited by the first loop bound in response to the second nested loop having a total number of iterations that exceeds a value of a hardware property of the computing system. After a penultimate iteration of the first nested loop has completed, one or more iterations of the second nested loop are performed for a final iteration of the first nested loop until an alternative loop bound is reached.

公开(公告)号：US20180341479A1

公开(公告)日：2018-11-29

申请号：US15903991

申请日：2018-02-23

Applicant: Google LLC

Inventor： Olivier Temam ,  Harshit Khaitan ,  Ravi Narayanaswami ,  Dong Hyuk Woo

IPC: G06F9/30 ,  G06F9/34 ,  G06F17/16 ,  G06F9/32

Abstract: Methods, systems, and apparatus, including an apparatus for accessing a N-dimensional tensor, the apparatus including, for each dimension of the N-dimensional tensor, a partial address offset value element that stores a partial address offset value for the dimension based at least on an initial value for the dimension, a step value for the dimension, and a number of iterations of a loop for the dimension. The apparatus includes a hardware adder and a processor. The processor obtains an instruction to access a particular element of the N-dimensional tensor. The N-dimensional tensor has multiple elements arranged across each of the N dimensions, where N is an integer that is equal to or greater than one. The processor determines, using the partial address offset value elements and the hardware adder, an address of the particular element and outputs data indicating the determined address for accessing the particular element of the N-dimensional tensor.

公开(公告)号：US10108538B1

公开(公告)日：2018-10-23

申请号：US15664842

申请日：2017-07-31

Applicant: Google LLC

Inventor： Olivier Temam ,  Harshit Khaitan ,  Ravi Narayanaswami ,  Dong Hyuk Woo

IPC: G06N5/00 ,  G06F12/02 ,  G06F12/1009 ,  G06N99/00 ,  G06N5/02

Abstract: Methods, systems, and apparatus, including an apparatus for accessing data. In some implementations, an apparatus includes address offset value elements that are each configured to store an address offset value. For each address offset value element, the apparatus can include address computation elements that each store a value used to determine the address offset value. One or more processors are configured to receive a program for performing computations using tensor elements of a tensor. The processor(s) can identify, in the program, a prologue or epilogue loop having a corresponding data array for storing values of the prologue or epilogue loop and populate, for a first address offset value element that corresponds to the prologue or epilogue loop, the address computation elements for the first address offset value element with respective values based at least on a number of iterations of the prologue or epilogue loop.

公开(公告)号：US20240078417A1

公开(公告)日：2024-03-07

申请号：US18217107

申请日：2023-06-30

Applicant: Google LLC

Inventor： Olivier Temam ,  Harshit Khaitan ,  Ravi Narayanaswami ,  Dong Hyuk Woo

IPC: G06N3/063 ,  G06F9/38 ,  G06F13/00 ,  G06F17/16 ,  G06N3/045 ,  G06N3/048

CPC classification number: G06N3/063 ,  G06F9/3887 ,  G06F9/3895 ,  G06F13/00 ,  G06F17/16 ,  G06N3/045 ,  G06N3/048

Abstract: One embodiment of an accelerator includes a computing unit; a first memory bank for storing input activations and a second memory bank for storing parameters used in performing computations, the second memory bank configured to store a sufficient amount of the neural network parameters on the computing unit to allow for latency below a specified level with throughput above a specified level. The computing unit includes at least one cell comprising at least one multiply accumulate (“MAC”) operator that receives parameters from the second memory bank and performs computations. The computing unit further includes a first traversal unit that provides a control signal to the first memory bank to cause an input activation to be provided to a data bus accessible by the MAC operator. The computing unit performs computations associated with at least one element of a data array, the one or more computations performed by the MAC operator.

公开(公告)号：US11422801B2

公开(公告)日：2022-08-23

申请号：US16239760

申请日：2019-01-04

Applicant: Google LLC

Inventor： Olivier Temam ,  Ravi Narayanaswami ,  Harshit Khaitan ,  Dong Hyuk Woo

IPC: G06F9/30 ,  G06F13/28 ,  G06N3/04 ,  G06N3/063 ,  G06F9/38

Abstract: A computing unit is disclosed, comprising a first memory bank for storing input activations and a second memory bank for storing parameters used in performing computations. The computing unit includes at least one cell comprising at least one multiply accumulate (“MAC”) operator that receives parameters from the second memory bank and performs computations. The computing unit further includes a first traversal unit that provides a control signal to the first memory bank to cause an input activation to be provided to a data bus accessible by the MAC operator. The computing unit performs one or more computations associated with at least one element of a data array, the one or more computations being performed by the MAC operator and comprising, in part, a multiply operation of the input activation received from the data bus and a parameter received from the second memory bank.

公开(公告)号：US11379707B2

公开(公告)日：2022-07-05

申请号：US15820704

申请日：2017-11-22

Applicant: Google LLC

Inventor： Ravi Narayanaswami ,  Dong Hyuk Woo ,  Olivier Temam ,  Harshit Khaitan

IPC: G06N5/04 ,  G06N3/04 ,  G06N3/063 ,  G06F13/28

Abstract: A computer-implemented method that includes receiving, by a processing unit, an instruction that specifies data values for performing a tensor computation. In response to receiving the instruction, the method may include, performing, by the processing unit, the tensor computation by executing a loop nest comprising a plurality of loops, wherein a structure of the loop nest is defined based on one or more of the data values of the instruction. The tensor computation can be at least a portion of a computation of a neural network layer. The data values specified by the instruction may comprise a value that specifies a type of the neural network layer, and the structure of the loop nest can be defined at least in part by the type of the neural network layer.

公开(公告)号：US10885434B2

公开(公告)日：2021-01-05

申请号：US16297091

申请日：2019-03-08

Applicant: Google LLC

Inventor： Olivier Temam ,  Harshit Khaitan ,  Ravi Narayanaswami ,  Dong Hyuk Woo

IPC: G06N3/08 ,  G06N20/00 ,  G06F8/41 ,  G06N3/063 ,  G06T1/20 ,  G06N3/04

Abstract: Methods, systems, and apparatus for accessing a N-dimensional tensor are described. In some implementations, a method includes, for each of one or more first iterations of a first nested loop, performing iterations of a second nested loop that is nested within the first nested loop until a first loop bound for the second nested loop is reached. A number of iterations of the second nested loop for the one or more first iterations of the first nested loop is limited by the first loop bound in response to the second nested loop having a total number of iterations that exceeds a value of a hardware property of the computing system. After a penultimate iteration of the first nested loop has completed, one or more iterations of the second nested loop are performed for a final iteration of the first nested loop until an alternative loop bound is reached.

公开(公告)号：US20200005128A1

公开(公告)日：2020-01-02

申请号：US16569607

申请日：2019-09-12

Applicant: Google LLC

Inventor： Olivier Temam ,  Harshit Khaitan ,  Ravi Narayanaswami ,  Dong Hyuk Woo

IPC: G06N3/063 ,  G06F9/38 ,  G06F17/16

Abstract: One embodiment of an accelerator includes a computing unit; a first memory bank for storing input activations and a second memory bank for storing parameters used in performing computations, the second memory bank configured to store a sufficient amount of the neural network parameters on the computing unit to allow for latency below a specified level with throughput above a specified level. The computing unit includes at least one cell comprising at least one multiply accumulate (“MAC”) operator that receives parameters from the second memory bank and performs computations. The computing unit further includes a first traversal unit that provides a control signal to the first memory bank to cause an input activation to be provided to a data bus accessible by the MAC operator. The computing unit performs computations associated with at least one element of a data array, the one or more computations performed by the MAC operator.