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公开(公告)号:US20190334830A1
公开(公告)日:2019-10-31
申请号:US15963296
申请日:2018-04-26
Applicant: Hewlett Packard Enterprise Development LP
Inventor: Frank R. Dropps , Joseph G. Tietz
IPC: H04L12/911 , H04L12/937
Abstract: Example implementations relate to arbitrating access to a shared resource for a plurality of data streams. An example implementation includes selecting a data stream from the plurality of data streams according to an arbitration scheme. A data packet of the selected data stream may be granted access to the shared resource. A source count associated with a source of the data packet may be adjusted, and the arbitration scheme may be blocked from selecting the data stream where the source count exceeds a threshold.
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公开(公告)号:US10331581B2
公开(公告)日:2019-06-25
申请号:US15483880
申请日:2017-04-10
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor: Frank R. Dropps , Michael E. Malewicki
Abstract: A high-performance computing system, method, and storage medium manage accesses to multiple memory modules of a computing node, the modules having different access latencies. The node allocates its resources into pools according to pre-determined memory access criteria. When another computing node requests a memory access, the node determines whether the request satisfies any of the criteria. If so, the associated pool of resources is selected for servicing the request; if not, a default pool is selected. The node then services the request if the pool of resources is sufficient. Otherwise, various error handling processes are performed. Each memory access criterion may relate to a memory address range assigned to a memory module, a type of request, a relationship between the nodes, a configuration of the requesting node, or a combination of these.
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公开(公告)号:US20190121780A1
公开(公告)日:2019-04-25
申请号:US15792644
申请日:2017-10-24
Applicant: Hewlett Packard Enterprise Development LP
Inventor: Frank R. Dropps
IPC: G06F15/173 , G06F12/0817
Abstract: A first node controller may include logic to direct the first node controller to: receive a noncoherent inter-processor communication from a source processor, remap the noncoherent inter-processor communication to a local address space of a destination processor and transmit the noncoherent inter-processor communication directly to a second node controller of the destination processor using an interconnect interface that also carries coherent communications.
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公开(公告)号:US10268630B1
公开(公告)日:2019-04-23
申请号:US15792644
申请日:2017-10-24
Applicant: Hewlett Packard Enterprise Development LP
Inventor: Frank R. Dropps
IPC: G06F12/00 , G06F15/173 , G06F12/0817 , G06F9/54
Abstract: A first node controller may include logic to direct the first node controller to: receive a noncoherent inter-processor communication from a source processor, remap the noncoherent inter-processor communication to a local address space of a destination processor and transmit the noncoherent inter-processor communication directly to a second node controller of the destination processor using an interconnect interface that also carries coherent communications.
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公开(公告)号:US12282662B2
公开(公告)日:2025-04-22
申请号:US17898189
申请日:2022-08-29
Applicant: Hewlett Packard Enterprise Development LP
Inventor: Thomas Edward McGee , Brian J. Johnson , Frank R. Dropps , Derek S. Schumacher , Stuart C. Haden , Michael S. Woodacre
IPC: G06F3/06 , G06F12/0817
Abstract: One aspect of the application can provide a system and method for replacing a failing node with a spare node in a non-uniform memory access (NUMA) system. During operation, in response to determining that a node-migration condition is met, the system can initialize a node controller of the spare node such that accesses to a memory local to the spare node are to be processed by the node controller, quiesce the failing node and the spare node to allow state information of processors on the failing node to be migrated to processors on the spare node, and subsequent to unquiescing the failing node and the spare node, migrate data from the failing node to the spare node while maintaining cache coherence in the NUMA system and while the NUMA system remains in operation, thereby facilitating continuous execution of processes previously executed on the failing node.
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公开(公告)号:US11188480B1
公开(公告)日:2021-11-30
申请号:US15930263
申请日:2020-05-12
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor: Frank R. Dropps , Thomas Edward McGee
IPC: G06F13/00 , G06F12/128 , G06F12/123 , G06F9/30 , G06F12/0815
Abstract: Systems and methods are provided for addressing die are inefficiencies associated with the use of redundant ternary content-addressable memory (TCAM) for facilitating error detection and correction. Only a portion of redundant TCAMs (or portions of the same TCAM) are reserved for modified coherency directory cache entries, while remaining portions are available for unmodified coherency directory cache entries. The amount of space reserved for redundant, modified coherency directory cache entries can be programmable and adaptable.
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公开(公告)号:US20200349077A1
公开(公告)日:2020-11-05
申请号:US16399378
申请日:2019-04-30
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor: Frank R. Dropps
IPC: G06F12/0817 , G06F12/123
Abstract: In exemplary aspects of managing the ejection of entries of a coherence directory cache, the directory cache includes directory cache entries that can store copies of respective directory entries from a coherency directory. Each of the directory cache entries is configured to include state and ownership information of respective memory blocks. Information is stored, which indicates if memory blocks are in an active state within a memory region of a memory. A request is received and includes a memory address of a first memory block. Based on the memory address in the request, a cache hit in the directory cache is detected. The request is determined to be a request to change the state of the first memory block to an invalid state. The ejection of a directory cache entry corresponding to the first memory block is managed based on ejection policy rules.
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公开(公告)号:US20200257066A1
公开(公告)日:2020-08-13
申请号:US16272785
申请日:2019-02-11
Applicant: Hewlett Packard Enterprise Development LP
Inventor: Mir Ashkan Seyedi , Frank R. Dropps
Abstract: Examples herein relate to optical interconnect topologies. In particular, implementations herein relate to optical interconnects that include a transmitter. The transmitter includes an optical source configured to emit light, a waveguide coupled to the optical source and configured to receive the emitted light from the optical source, a plurality of ring resonators coupled to the waveguide, each ring modulator corresponding to a different channel of the optical source, and wherein each ring resonator is configured to be tuned to a single wavelength of the emitted light different from the other ring resonators. The transmitter further includes a plurality of optical couplers, each optical coupler coupled to a drop port of a respective ring resonator, and wherein each optical coupler is configured to be coupled to an optical fiber and to couple the single wavelength of the emitted light from each respective ring resonator to the optical fiber.
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公开(公告)号:US10592465B2
公开(公告)日:2020-03-17
申请号:US15794471
申请日:2017-10-26
Applicant: Hewlett Packard Enterprise Development LP
Inventor: Frank R. Dropps , Eric C. Fromm
IPC: G06F12/08 , G06F15/173 , G06F12/0813 , G06F12/0815
Abstract: A node controller for a first processor socket group may include a node memory storing a coherence directory and logic. Logic may cause the node controller to: receive a memory operation request directly from a second processor socket group, follow a coherence protocol based on the memory operation request and the coherence directory and directly access a socket group memory of the first processor socket group based on the request.
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公开(公告)号:US20190129884A1
公开(公告)日:2019-05-02
申请号:US15794471
申请日:2017-10-26
Applicant: Hewlett Packard Enterprise Development LP
Inventor: Frank R. Dropps , Eric C. Fromm
IPC: G06F15/173 , G06F12/0815 , G06F12/0813
Abstract: A node controller for a first processor socket group may include a node memory storing a coherence directory and logic. Logic may cause the node controller to: receive a memory operation request directly from a second processor socket group, follow a coherence protocol based on the memory operation request and the coherence directory and directly access a socket group memory of the first processor socket group based on the request.
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