公开(公告)号：US10944694B2

公开(公告)日：2021-03-09

申请号：US15370485

申请日：2016-12-06

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Joseph G. Tietz ,  Eric C. Fromm

IPC: H04L12/937

Abstract: This patent application relates generally to a predictive arbitration circuit for use in arbitrating access by a number of data streams to a shared resource managed by a destination (arbiter), where each data stream is associated with a number of sources competing for the shared resource, and the destination provides access to the shared resource based on the number of sources competing for the shared resource rather than just on the number of data streams. Among other things, this approach can more fairly distribute access to the shared resource among the competing sources.

公开(公告)号：US10592465B2

公开(公告)日：2020-03-17

申请号：US15794471

申请日：2017-10-26

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Frank R. Dropps ,  Eric C. Fromm

IPC: G06F12/08 ,  G06F15/173 ,  G06F12/0813 ,  G06F12/0815

Abstract: A node controller for a first processor socket group may include a node memory storing a coherence directory and logic. Logic may cause the node controller to: receive a memory operation request directly from a second processor socket group, follow a coherence protocol based on the memory operation request and the coherence directory and directly access a socket group memory of the first processor socket group based on the request.

公开(公告)号：US20190129884A1

公开(公告)日：2019-05-02

申请号：US15794471

申请日：2017-10-26

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Frank R. Dropps ,  Eric C. Fromm

IPC: G06F15/173 ,  G06F12/0815 ,  G06F12/0813

Abstract: A node controller for a first processor socket group may include a node memory storing a coherence directory and logic. Logic may cause the node controller to: receive a memory operation request directly from a second processor socket group, follow a coherence protocol based on the memory operation request and the coherence directory and directly access a socket group memory of the first processor socket group based on the request.

公开(公告)号：US20180018196A1

公开(公告)日：2018-01-18

申请号：US15650357

申请日：2017-07-14

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Steven J. Dean ,  Michael Woodacre ,  Randal S. Passint ,  Eric C. Fromm ,  Thomas E. McGee ,  Michael E. Malewicki ,  Kirill Malkin

IPC: G06F9/455 ,  G06F9/50 ,  G06Q10/06 ,  H04L29/08

CPC classification number: G06F9/45558 ,  G06F9/50 ,  G06F9/5077 ,  G06F9/54 ,  G06F2009/45595 ,  G06Q10/06 ,  H04L29/08315 ,  H04L67/1042

Abstract: A high performance computing (HPC) system has an architecture that separates data paths used by compute nodes exchanging computational data from the data paths used by compute nodes to obtain computational work units and save completed computations. The system enables an improved method of saving checkpoint data, and an improved method of using an analysis of the saved data to assign particular computational work units to particular compute nodes. The system includes a compute fabric and compute nodes that cooperatively perform a computation by mutual communication using the compute fabric. The system also includes a local data fabric that is coupled to the compute nodes, a memory, and a data node. The data node is configured to retrieve data for the computation from an external bulk data storage, and to store its work units in the memory for access by the compute nodes.

公开(公告)号：US10721185B2

公开(公告)日：2020-07-21

申请号：US15370508

申请日：2016-12-06

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Joseph G. Tietz ,  Eric C. Fromm

IPC: H04L12/937 ,  H04L29/06 ,  H04L29/08 ,  H04L12/875 ,  H04L12/873 ,  H04L12/861 ,  H04L12/933 ,  H04L12/865 ,  H04L12/863 ,  H04L12/26

Abstract: This patent application relates generally to an age-based arbitration circuit for use in arbitrating access by a number of data streams to a shared resource managed by a destination (arbiter), in which age-based determinations are performed at the input sources of the data streams in order to designate certain packets as high-priority packets based on packet ages, and the destination expedites processing of the high-priority packets. Among other things, this approach offloads the age-based determinations from the destination, where they otherwise can cause delays in processing packets.

公开(公告)号：US10521260B2

公开(公告)日：2019-12-31

申请号：US15650357

申请日：2017-07-14

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Steven J. Dean ,  Michael Woodacre ,  Randal S. Passint ,  Eric C. Fromm ,  Thomas E. McGee ,  Michael E. Malewicki ,  Kirill Malkin

IPC: G06F9/46 ,  G06F9/455 ,  G06F9/50 ,  G06Q10/06 ,  G06F9/54 ,  H04L29/08

Abstract: A high performance computing (HPC) system has an architecture that separates data paths used by compute nodes exchanging computational data from the data paths used by compute nodes to obtain computational work units and save completed computations. The system enables an improved method of saving checkpoint data, and an improved method of using an analysis of the saved data to assign particular computational work units to particular compute nodes. The system includes a compute fabric and compute nodes that cooperatively perform a computation by mutual communication using the compute fabric. The system also includes a local data fabric that is coupled to the compute nodes, a memory, and a data node. The data node is configured to retrieve data for the computation from an external bulk data storage, and to store its work units in the memory for access by the compute nodes.