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    LOGIC CIRCUITRY
    13.
    发明申请
    LOGIC CIRCUITRY 有权

    公开(公告)号：US20210334392A1

    公开(公告)日：2021-10-28

    申请号：US16495248

    申请日：2018-12-03

    Applicant: Hewlett-Packard Development Company, L.P.

    Inventor： Stephen D. PANSHIN ,  Jefferson P. WARD ,  Scott A. LINN ,  James Michael GARDNER

    IPC: G06F21/60 ,  G06F21/44 ,  G06F21/84 ,  B41J2/175

    Abstract: In an example, a logic circuitry package is configured to communicate with a print apparatus logic circuit. The logic circuitry package may be configured to respond to communications sent to a first address and to at least one second address. The logic circuitry package may comprise a first logic circuit, wherein the first address is an address for the first logic circuit. The package may be configured such that, in response to a first command indicative of a task and a first time period sent to the first address, the package is accessible via at least one second address for a duration of the time period.

    LOGIC CIRCUITRY PACKAGE
    14.
    发明申请
    LOGIC CIRCUITRY PACKAGE 有权

    公开(公告)号：US20210213747A1

    公开(公告)日：2021-07-15

    申请号：US16767589

    申请日：2019-12-03

    Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

    Inventor： Jefferson P. WARD

    IPC: B41J2/175 ,  G06F13/42

    Abstract: A logic circuitry package for a print apparatus component includes an interface to communicate with a print apparatus logic circuit, and at least one logic circuit. The at least one logic circuit is configured to receive, via the interface, a command series addressed to a first default address and a second default address, and transmit, via the interface, at least one response in response to at least one command of the command series. The at least one logic circuit is configured to receive, via the interface, an other command series addressed to an other first default address and subsequently, the second default address, and transmit, via the interface, at least one other response in response to at least one other command of the other command series.

    SUPPLY AUTHENTICATION VIA TIMING CHALLENGE RESPONSE
    15.
    发明申请
    SUPPLY AUTHENTICATION VIA TIMING CHALLENGE RESPONSE 有权
    供应认证通过时间挑战回应

    公开(公告)号：US20160214391A1

    公开(公告)日：2016-07-28

    申请号：US14913982

    申请日：2013-08-30

    Applicant: Hewlett-Packard Development Company, L.P.

    Inventor： Jefferson P. WARD ,  Stephen D. PANSHIN

    IPC: B41J2/175 ,  H04L9/32

    CPC classification number: B41J2/17546 ,  G03G15/0863 ,  G06F21/44 ,  G06F2221/2103 ,  G06F2221/2151 ,  H04L9/3271 ,  H04L63/0876

    Abstract: In an example implementation, an authentication system includes a printer having a controller and a memory. The authentication system also includes an authentication algorithm stored in the memory and executable on the controller to issue a cryptographic timing challenge, and to authenticate a print supply cartridge when the cartridge provides a challenge response corresponding to an expected response within an expected time window.

    Abstract translation: 在示例实现中，认证系统包括具有控制器和存储器的打印机。 认证系统还包括存储在存储器中并且可在控制器上执行的认证算法，以发出加密定时挑战，并且当盒提供与预期时间窗口内的预期响应相对应的质询响应时，对打印供应盒进行认证。

    LOGIC CIRCUITRY
    17.
    发明申请
    LOGIC CIRCUITRY 有权

    公开(公告)号：US20210221125A1

    公开(公告)日：2021-07-22

    申请号：US16771092

    申请日：2018-12-03

    Applicant: Hewlett-Packard Development Company, L.P.

    Inventor： Stephen D. PANSHIN ,  Jefferson P. WARD ,  Scott A. LINN ,  James Michael GARDNER

    IPC: B41J2/045

    Abstract: In an example, a logic circuitry package is configured to be addressable via a first address and at least one second address and comprises a first logic circuit. The first address may be an address for the first logic circuit, and the package may be configured such that, in response to a first command indicative of a first command time period sent to the first address, the package is accessible via at least one second address for a duration of the first command time period; and in response to a second command indicative of a second command time period sent to the first address, the first logic circuit is to, for a duration of the second command time period, disregard traffic sent to the first address.

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