公开(公告)号：US12073261B2

公开(公告)日：2024-08-27

申请号：US18477117

申请日：2023-09-28

Applicant: Huawei Technologies Co., Ltd.

Inventor： Xiangyi Zhu ,  Hou Fun Lam

IPC: G06F9/46 ,  G06F9/52

CPC classification number: G06F9/52

Abstract: In a synchronization method, a first processor creates a first synchronization object for a first synchronization event. The first synchronization object includes an identifier of a first synchronization register. A value of the first synchronization register includes a first value or a second value. The first value is used to indicate that the first synchronization event does not occur, and the second value is used to indicate that the first synchronization event occurs. The first processor includes a first CPU. The second processor determines, based on the value of the first synchronization register, whether the first synchronization event occurs. The second processor includes a first NPU.

公开(公告)号：US11941434B2

公开(公告)日：2024-03-26

申请号：US17097211

申请日：2020-11-13

Applicant: Huawei Technologies Co., Ltd.

Inventor： Wei Li ,  Xiong Gao ,  Hou Fun Lam ,  Tao Ma

IPC: G06F9/48 ,  G06F9/38

CPC classification number: G06F9/4881 ,  G06F9/3838

Abstract: A task processing method, a processing apparatus, and a computer system are provided. Implementation of the method includes: generating, by a first processing apparatus, a plurality of tasks, and determining task description information of the plurality of tasks, where the task description information of the plurality of tasks is used to indicate a dependency relationship between the plurality of tasks; sending an instruction to a second processing apparatus, where the instruction includes the plurality of tasks and the task description information of the plurality of tasks; and receiving the instruction, and processing the plurality of tasks based on the dependency relationship between the plurality of tasks. The method can effectively reduce a waiting delay, fully exploit a computing capability of an acceleration chip, and improve task processing efficiency.

公开(公告)号：US11934481B2

公开(公告)日：2024-03-19

申请号：US17725492

申请日：2022-04-20

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Hu Liu ,  Heng Liao ,  Jiajin Tu ,  Honghui Yuan ,  Hou Fun Lam ,  Fan Zhu

IPC: G06F17/16

CPC classification number: G06F17/16

Abstract: Embodiments of the present invention disclose a matrix multiplier, and relate to the field of data computing technologies, so as to divide two matrices into blocks for computation. The matrix multiplier includes: a first memory, a second memory, an operation circuit, and a controller, where the operation circuit, the first memory, and the second memory may perform data communication by using a bus; and the controller is configured to control, according to a preset program or instruction, a first matrix and a second matrix to be divided into blocks, and control the operation circuit to perform a multiplication operation on corresponding blocks in the first memory and the second memory based on block division results of the controller. The matrix multiplier may be configured to perform a multiplication operation on two matrices.

公开(公告)号：US11334648B2

公开(公告)日：2022-05-17

申请号：US16915915

申请日：2020-06-29

Applicant: HUAWEI TECHNOLOGIES CO.,LTD.

Inventor： Hu Liu ,  Heng Liao ,  Jiajin Tu ,  Honghui Yuan ,  Hou Fun Lam ,  Fan Zhu

IPC: G06F17/16

Abstract: Embodiments of the present invention disclose a matrix multiplier, and relate to the field of data computing technologies, so as to divide two matrices into blocks for computation. The matrix multiplier includes: a first memory, a second memory, an operation circuit, and a controller, where the operation circuit, the first memory, and the second memory may perform data communication by using a bus; and the controller is configured to control, according to a preset program or instruction, a first matrix and a second matrix to be divided into blocks, and control the operation circuit to perform a multiplication operation on corresponding blocks in the first memory and the second memory based on block division results of the controller. The matrix multiplier may be configured to perform a multiplication operation on two matrices.

公开(公告)号：US20210064425A1

公开(公告)日：2021-03-04

申请号：US17097211

申请日：2020-11-13

Applicant: Huawei Technologies Co., Ltd.

Inventor： Wei Li ,  Xiong Gao ,  Hou Fun Lam ,  Tao Ma

IPC: G06F9/48 ,  G06F9/38

Abstract: A task processing method, a processing apparatus, and a computer system are provided. Implementation of the method includes: generating, by a first processing apparatus, a plurality of tasks, and determining task description information of the plurality of tasks, where the task description information of the plurality of tasks is used to indicate a dependency relationship between the plurality of tasks; sending an instruction to a second processing apparatus, where the instruction includes the plurality of tasks and the task description information of the plurality of tasks; and receiving the instruction, and processing the plurality of tasks based on the dependency relationship between the plurality of tasks. The method can effectively reduce a waiting delay, fully exploit a computing capability of an acceleration chip, and improve task processing efficiency.