公开(公告)号：US11823303B2

公开(公告)日：2023-11-21

申请号：US16932768

申请日：2020-07-19

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Luping Cui ,  Jiajin Tu ,  Hu Liu ,  Honghui Yuan ,  Heng Liao ,  Hou Fun Lam ,  Bing Li

IPC: G06F17/16 ,  G06T1/20 ,  G06N3/02 ,  G06V10/82 ,  G06V10/44

CPC classification number: G06T1/20 ,  G06F17/16 ,  G06N3/02 ,  G06V10/454 ,  G06V10/82

Abstract: A data processing method and apparatus are disclosed. In various embodiments, R groups of proposal region sequences are obtained. Each group of proposal region sequence includes a plurality of proposal regions. In those embodiments, a VRPAC instruction is invoked to calculate an area of each proposal region in each group of proposal region sequence. For a jth group of proposal region sequence in the R groups of proposal region sequences, a VIOU instruction and a VAADD instruction are invoked to determine j suppression matrices of the jth group of proposal region sequence and determine a suppression vector of the jth group of proposal region sequence based on the j suppression matrices. In those embodiments, an unsuppressed proposal region is determined based on a suppression vector of each group of proposal region sequence.

公开(公告)号：US20240152471A1

公开(公告)日：2024-05-09

申请号：US18416413

申请日：2024-01-18

Applicant: Huawei Technologies Co., Ltd.

Inventor： Leilei Liu ,  Mengjie Bai ,  Honghui Yuan

IPC: G06F13/28

CPC classification number: G06F13/28

Abstract: This application relates to a data format conversion apparatus and method. The data format conversion apparatus is located in a DMA module of a processor. A data format that is of tensor data and that is supported by the processor is a first data format. The DMA module includes: a DMA controller DMAC. If a second data format of tensor data stored in an external memory is different from the first data format, the DMAC is configured to convert, in a process of transmitting to-be-converted tensor data between a memory of the processor and the external memory, the to-be-converted tensor data from the first data format into the second data format or from the second data format into the first data format, to obtain converted tensor data.

公开(公告)号：US10432506B2

公开(公告)日：2019-10-01

申请号：US15824032

申请日：2017-11-28

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Xianbo Chen ,  Honghui Yuan ,  Binbin Yao

IPC: H04L12/725 ,  G06F9/48 ,  H04L12/741 ,  H04L12/715 ,  G06F9/54

Abstract: A data processing method is disclosed, the method includes: receiving a request message that is sent from a host service layer and transparently transmitted through a host driver layer, where the request message includes at least one acceleration type identifier and to-be-acceleratedly-processed service data, and each acceleration type identifier corresponds to one type of accelerated processing; and performing at least one type of accelerated processing in a one-to-one correspondence with the at least one acceleration type identifier on the service data. In the method, interaction between the host service layer and the hardware processing unit does not need coordination of a specialized driver, so that dependence on a specific underlying driver for a service layer may be shielded.

公开(公告)号：US12014264B2

公开(公告)日：2024-06-18

申请号：US17005488

申请日：2020-08-28

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Zhanying He ,  Bin Xu ,  Honghui Yuan

IPC: G06F7/556 ,  G06F7/485 ,  G06F7/487 ,  G06F7/57 ,  G06N3/063

CPC classification number: G06N3/063 ,  G06F7/485 ,  G06F7/4876 ,  G06F7/556 ,  G06F7/57 ,  G06F2207/4824

Abstract: A data processing circuit is disclosed. The data processing circuit relates to the field of digital circuits, and includes a first computing circuit and an input control circuit. The first computing circuit includes one or more computing sub-circuits. Each computing sub-circuit includes a first addition operation circuit, a multiplication operation circuit, a first comparison operation circuit, and a first nonlinear operation circuit. The first nonlinear operation circuit includes at least one of an exponential operation circuit and a logarithmic operation circuit. The input control circuit is configured to: control the first computing circuit to read input data and an input parameter, and control, according to a received first instruction, the operation circuit in the computing sub-circuit included in the first computing circuit, to perform an operation on the input data and the input parameter.

公开(公告)号：US20200334322A1

公开(公告)日：2020-10-22

申请号：US16915915

申请日：2020-06-29

Applicant: HUAWEI TECHNOLOGIES CO.,LTD.

Inventor： Hu Liu ,  Heng Liao ,  Jiajin Tu ,  Honghui Yuan ,  Haoxun Lin ,  Fan Zhu

IPC: G06F17/16

Abstract: Embodiments of the present invention disclose a matrix multiplier, and relate to the field of data computing technologies, so as to divide two matrices into blocks for computation. The matrix multiplier includes: a first memory, a second memory, an operation circuit, and a controller, where the operation circuit, the first memory, and the second memory may perform data communication by using a bus; and the controller is configured to control, according to a preset program or instruction, a first matrix and a second matrix to be divided into blocks, and control the operation circuit to perform a multiplication operation on corresponding blocks in the first memory and the second memory based on block division results of the controller. The matrix multiplier may be configured to perform a multiplication operation on two matrices.

公开(公告)号：US11934481B2

公开(公告)日：2024-03-19

申请号：US17725492

申请日：2022-04-20

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Hu Liu ,  Heng Liao ,  Jiajin Tu ,  Honghui Yuan ,  Hou Fun Lam ,  Fan Zhu

IPC: G06F17/16

CPC classification number: G06F17/16

Abstract: Embodiments of the present invention disclose a matrix multiplier, and relate to the field of data computing technologies, so as to divide two matrices into blocks for computation. The matrix multiplier includes: a first memory, a second memory, an operation circuit, and a controller, where the operation circuit, the first memory, and the second memory may perform data communication by using a bus; and the controller is configured to control, according to a preset program or instruction, a first matrix and a second matrix to be divided into blocks, and control the operation circuit to perform a multiplication operation on corresponding blocks in the first memory and the second memory based on block division results of the controller. The matrix multiplier may be configured to perform a multiplication operation on two matrices.

公开(公告)号：US11334648B2

公开(公告)日：2022-05-17

申请号：US16915915

申请日：2020-06-29

Applicant: HUAWEI TECHNOLOGIES CO.,LTD.

Inventor： Hu Liu ,  Heng Liao ,  Jiajin Tu ,  Honghui Yuan ,  Hou Fun Lam ,  Fan Zhu

IPC: G06F17/16

Abstract: Embodiments of the present invention disclose a matrix multiplier, and relate to the field of data computing technologies, so as to divide two matrices into blocks for computation. The matrix multiplier includes: a first memory, a second memory, an operation circuit, and a controller, where the operation circuit, the first memory, and the second memory may perform data communication by using a bus; and the controller is configured to control, according to a preset program or instruction, a first matrix and a second matrix to be divided into blocks, and control the operation circuit to perform a multiplication operation on corresponding blocks in the first memory and the second memory based on block division results of the controller. The matrix multiplier may be configured to perform a multiplication operation on two matrices.

公开(公告)号：US20220245218A1

公开(公告)日：2022-08-04

申请号：US17725492

申请日：2022-04-20

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Hu Liu ,  Heng Liao ,  Jiajin Tu ,  Honghui Yuan ,  Hou Fun Lam ,  Fan Zhu

IPC: G06F17/16

Abstract: Embodiments of the present invention disclose a matrix multiplier, and relate to the field of data computing technologies, so as to divide two matrices into blocks for computation. The matrix multiplier includes: a first memory, a second memory, an operation circuit, and a controller, where the operation circuit, the first memory, and the second memory may perform data communication by using a bus; and the controller is configured to control, according to a preset program or instruction, a first matrix and a second matrix to be divided into blocks, and control the operation circuit to perform a multiplication operation on corresponding blocks in the first memory and the second memory based on block division results of the controller. The matrix multiplier may be configured to perform a multiplication operation on two matrices.