Gate Drive Circuit, Display Device and Method for Driving Gate Drive Circuit

    公开(公告)号:US20200035138A1

    公开(公告)日:2020-01-30

    申请号:US16385189

    申请日:2019-04-16

    IPC分类号: G09G3/20 G11C19/28

    摘要: A gate drive circuit, a display device and a driving method are provided. The gate drive circuit includes a scan signal generation circuit and output control circuits in N stages. The scan signal generation circuit includes first output terminals in 2N stages, and is configured to output scan pulse signals in an order at the first output terminals in 2N stages; each of the output control circuits in N stages includes an input terminal, a first control terminal, a second control terminal, a second output terminal, and a bootstrap circuit, and is configured to control the bootstrap circuit, under control of a first control signal received by the first control terminal, an input signal received by the input terminal, and a second control signal received by the second control terminal, to output an output pulse signal with different pulse levels at the second output terminal.

    Shift register unit, method of driving shift register unit, gate drive circuit, and display device

    公开(公告)号:US11335293B2

    公开(公告)日:2022-05-17

    申请号:US16491910

    申请日:2019-02-18

    IPC分类号: G09G3/36

    摘要: A shift register unit, a method of driving a shift register unit, a gate drive circuit, and a display device are provided. The shift register unit includes an input circuit, an output circuit, a first reset circuit, and a reset control circuit. The input circuit is configured to control a level of a first node; the output circuit is configured to output a clock signal to an output terminal; the first reset circuit is configured to reset the first node; and the reset control circuit is configured to input the first reset signal to the first reset circuit in response to a reset control signal and a reference signal, to turn on the first reset circuit and the reset control circuit is further configured to enable an amplitude of a level of the first reset signal to be larger than an amplitude of a level of the reference signal.

    Shift register unit, method of driving the same, gate driving circuit and display device

    公开(公告)号:US10978168B2

    公开(公告)日:2021-04-13

    申请号:US16640201

    申请日:2019-08-05

    IPC分类号: G09G3/22 G11C19/28

    摘要: A shift register unit, a method of driving the same, a gate driving circuit and a display device are provided. The shift register unit includes a pull-up node control circuit, a first pull-down node control circuit, a second pull-down node control circuit, a pull-down node switching control circuit, and a gate driving output circuit. The pull-down node switching control circuit is configured to control the first control voltage signal to be written into the first pull-down node and control the second control voltage signal to be written into the second pull-down node under the control of a frame reset control signal. The gate driving output circuit is configured to control a gate driving signal outputted by a gate driving signal output terminal under the control of the voltage signal of the pull-up node, the voltage signal of the first pull-down node, and the voltage signal of the second pull-down node.

    Shift register unit, gate driving circuit, display device and driving method

    公开(公告)号:US10950320B2

    公开(公告)日:2021-03-16

    申请号:US16535412

    申请日:2019-08-08

    IPC分类号: G11C19/28 G09G3/20

    摘要: A shift register unit including a first output circuit configured to transfer a clock signal at a clock signal terminal to a signal output terminal as an output signal in response to a first node being at an active potential, a second output circuit configured to transfer the clock signal at the clock signal terminal to a carry output terminal as a carry output signal in response to the first node being at the active potential, and a delay circuit configured to generate a delayed version of a carry input signal in response to the carry input signal at a carry input terminal being active, and to transfer an inactive voltage at a first voltage terminal to the signal output terminal in response to the delayed version of the carry input signal being active.

    Gate drive circuit, display device and method for driving gate drive circuit

    公开(公告)号:US10748465B2

    公开(公告)日:2020-08-18

    申请号:US16385189

    申请日:2019-04-16

    IPC分类号: G09G3/20 G11C19/28

    摘要: A gate drive circuit, a display device and a driving method are provided. The gate drive circuit includes a scan signal generation circuit and output control circuits in N stages. The scan signal generation circuit includes first output terminals in 2N stages, and is configured to output scan pulse signals in an order at the first output terminals in 2N stages; each of the output control circuits in N stages includes an input terminal, a first control terminal, a second control terminal, a second output terminal, and a bootstrap circuit, and is configured to control the bootstrap circuit, under control of a first control signal received by the first control terminal, an input signal received by the input terminal, and a second control signal received by the second control terminal, to output an output pulse signal with different pulse levels at the second output terminal.

    Gate drive circuit, display device and method for driving gate drive circuit

    公开(公告)号:US10699620B2

    公开(公告)日:2020-06-30

    申请号:US16385189

    申请日:2019-04-16

    IPC分类号: G09G3/20 G11C19/28

    摘要: A gate drive circuit, a display device and a driving method are provided. The gate drive circuit includes a scan signal generation circuit and output control circuits in N stages. The scan signal generation circuit includes first output terminals in 2N stages, and is configured to output scan pulse signals in an order at the first output terminals in 2N stages; each of the output control circuits in N stages includes an input terminal, a first control terminal, a second control terminal, a second output terminal, and a bootstrap circuit, and is configured to control the bootstrap circuit, under control of a first control signal received by the first control terminal, an input signal received by the input terminal, and a second control signal received by the second control terminal, to output an output pulse signal with different pulse levels at the second output terminal.