公开(公告)号：US5930646A

公开(公告)日：1999-07-27

申请号：US169435

申请日：1998-10-09

申请人： Henry Gerung ,  Igor V. Peidous ,  Thomas Schuelke ,  Andrew Kuswatno

发明人： Henry Gerung ,  Igor V. Peidous ,  Thomas Schuelke ,  Andrew Kuswatno

IPC分类号： H01L21/3105 ,  H01L21/762 ,  H01L21/76

CPC分类号： H01L21/31053 ,  H01L21/31051 ,  H01L21/76229

摘要： The invention is an improved process for forming isolations of uniform thickness in narrow and wide trenches. The process begins by forming a pad layer on a semiconductor substrate. A first barrier layer is formed on the pad layer. The first barrier layer and pad layer are patterned forming openings, thereby exposing the substrate surface. The substrate is then etched through the openings to form shallow trenches in the substrate. The trenches generally falling into two ranges of width: narrow trenches having widths in the range between 0.3 .mu.m and 1.0 .mu.m; and wide trenches having widths greater than 1.0 .mu.m. A thin oxide film is grown on the sidewalls and bottoms of the trenches. A gap-fill dielectric layer is formed on the thin oxide film. A polysilicon layer is grown on the gap-fill dielectric layer. The polysilicon layer acts as a stop during CMP, providing additional protection of the gap-fill dielectric layer in the wide trenches. A planarizing material layer is formed on the polysilicon layer. The planarizing material layer, polysilicon layer and gap-fill dielectric layer are planarized to the level of the first barrier layer using chemical mechanical polishing (CMP). The residual planarizing material is then stripped. The polysilicon layer is oxidized forming a novel second dielectric oxide layer in an oxidizing atmosphere. The dielectric layer is densified, preferably in the same oxidizing atmosphere, forming an isolation layer with uniform thickness in the narrow trenches and the wide trenches. The stress developed during conversion of the polysilicon layer to a novel second dielectric oxide layer compensates for the stress due to densification of the dielectric layer.

摘要翻译： 本发明是在狭窄和宽沟槽中形成均匀厚度的隔离的改进方法。 该过程开始于在半导体衬底上形成焊盘层。 在衬垫层上形成第一阻挡层。 第一阻挡层和衬垫层被图案化形成开口，从而暴露衬底表面。 然后通过开口蚀刻衬底，以在衬底中形成浅沟槽。 沟槽一般落在两个宽度范围内：宽度在0.3μm至1.0μm之间的窄沟槽; 宽度大于1.0μm的宽沟槽。 在沟槽的侧壁和底部生长薄氧化膜。 在薄氧化膜上形成间隙填充电介质层。 在间隙填充介电层上生长多晶硅层。 多晶硅层在CMP期间用作停止，为宽沟槽中的间隙填充电介质层提供额外的保护。 平坦化材料层形成在多晶硅层上。 使用化学机械抛光（CMP）将平坦化材料层，多晶硅层和间隙填充介电层平坦化为第一势垒层的水平。 然后剥离剩余的平坦化材料。 多晶硅层被氧化，在氧化气氛中形成新的第二电介质氧化物层。 电介质层被致密化，优选在相同的氧化气氛中，在窄沟槽和宽沟槽中形成均匀厚度的隔离层。 在将多晶硅层转化为新颖的第二电介质氧化物层期间产生的应力补偿了由于介电层的致密化引起的应力。