公开(公告)号：US5519659A

公开(公告)日：1996-05-21

申请号：US408256

申请日：1995-03-22

申请人： Susumu Tanida ,  Kazutoshi Hirayama ,  Tomio Suzuki ,  Masanori Hayashikoshi

发明人： Susumu Tanida ,  Kazutoshi Hirayama ,  Tomio Suzuki ,  Masanori Hayashikoshi

IPC分类号： G11C29/26 ,  G11C29/50 ,  G11C7/00

CPC分类号： G11C29/50 ,  G11C29/26 ,  G06F2201/81 ,  G11C11/401 ,  G11C2029/5004 ,  G11C2029/5006

摘要： When a disturb refresh mode is detected by a mode detecting circuit, a row decoder control circuit simultaneously activates every several word lines of a memory cell array of a block selected by an operation block selecting circuit through a row decoder and a driving circuit, reads out data written in a normal mode, and determines a memory cell having a threshold value lower than that of a design value upon determination of match of read data and written data.

摘要翻译： 当通过模式检测电路检测到干扰刷新模式时，行解码器控制电路通过行解码器和驱动电路同时激活由操作块选择电路选择的块的存储单元阵列的每几条字线，读出 以正常模式写入的数据，并且在确定读取数据和写入数据的匹配时，确定具有低于设计值的阈值的阈值的存储单元。

公开(公告)号：US06301190B1

公开(公告)日：2001-10-09

申请号：US09606413

申请日：2000-06-29

申请人： Mitsunori Tsujino ,  Kazutoshi Hirayama ,  Kyoji Yamasaki

发明人： Mitsunori Tsujino ,  Kazutoshi Hirayama ,  Kyoji Yamasaki

IPC分类号： G11C800

CPC分类号： G11C29/48

摘要： A semiconductor memory device uses in a test mode a clock signal from a tester to allow a test clock conversion circuit and a DLL circuit to generate a rapid internal clock. The internal clock is applied to serial parallel conversion circuits subjecting received, packetized data to serial parallel conversion, and an interface circuit receiving and decoding outputs from the serial-parallel conversion circuits and outputting a command such as ACT to a DRAM core. Furthermore, an internal packet generation circuit uses the internal clock to rapidly generate a testing packet signal. Thus the device's operation can be checked with a low speed tester, without externally receiving a rapid packet signal.

摘要翻译： 半导体存储器件在测试模式中使用来自测试器的时钟信号，以允许测试时钟转换电路和DLL电路产生快速的内部时钟。 将内部时钟应用于串行并行转换电路，其对接收的分组化数据进行串行并行转换，以及接口电路，从串行/并行转换电路接收和解码输出，并将诸如ACT的命令输出到DRAM内核。 此外，内部分组产生电路使用内部时钟来快速生成测试分组信号。 因此，可以用低速测试仪检查设备的操作，而无需外部接收快速分组信号。

公开(公告)号：US5343429A

公开(公告)日：1994-08-30

申请号：US919415

申请日：1992-07-27

申请人： Akio Nakayama ,  Kazutoshi Hirayama

发明人： Akio Nakayama ,  Kazutoshi Hirayama

IPC分类号： G11C29/00 ,  G11C7/00

CPC分类号： G11C29/835

摘要： In a semiconductor memory device having a spare memory cell array and a spare column decoder and a spare row decoder as redundant circuits, redundancy detecting circuits for testing to see whether the redundant circuits are used or not after completion of the semiconductor memory device as a product are set so as to be capable of providing particular current signals or voltage signals, which indicate that the redundant circuits are used to predetermined external terminals, in response to an output signal at a predetermined logic level from a spare row decoder activating circuit or a spare column decoder activating circuit. When an external address signal is supplied to the semiconductor memory device, a signal at a logic level according to whether the redundant circuits are used or not is automatically latched in the redundancy detecting circuits in response to an output signal of the spare row decoder activating circuit or the spare column decoder activating circuit, so that it becomes unnecessary to set the state of electric connection in the redundancy detecting circuits according to whether the redundant circuits are used or not in manufacture.

摘要翻译： 在具有备用存储单元阵列和备用列解码器和备用行解码器作为冗余电路的半导体存储器件中，冗余检测电路用于在半导体存储器件完成后测试是否使用冗余电路作为产品 被设置为能够响应于来自备用行解码器激活电路或备用电路的预定逻辑电平的输出信号，提供指示将冗余电路用于预定外部端子的特定电流信号或电压信号 列解码器激活电路。 当向半导体存储器件提供外部地址信号时，响应于备用行解码器激活电路的输出信号，自动锁存冗余检测电路中根据冗余电路是否使用逻辑电平的信号 或备用列解码器激活电路，使得根据在制造中是否使用冗余电路，不需要在冗余检测电路中设置电连接的状态。

公开(公告)号：US5111078A

公开(公告)日：1992-05-05

申请号：US758704

申请日：1991-09-09

申请人： Hiroshi Miyamoto ,  Kazutoshi Hirayama

发明人： Hiroshi Miyamoto ,  Kazutoshi Hirayama

IPC分类号： G11C11/413 ,  G11C8/06 ,  G11C8/18 ,  G11C11/408 ,  H03K3/356 ,  H03K19/0185

CPC分类号： G11C8/06 ,  G11C8/18 ,  H03K3/356104

摘要： An address buffer circuit comprises a flip-flop circuit having first and second input nodes and connected between a power-supply potential and a ground potential. In addition, first, second and third transistors are connected in series in that order from the side of the ground between the first input node and the ground potential, to constitute a first input circuit, and fourth, fifth and sixth transistors are connected in series in that order from the side of the ground between the second input node and the ground potential, to constitute a second input circuit. An external address signal is applied to a control terminal of the first transistor, and a reference potential is applied to a control terminal of the fourth transistor. At the time of operating the address buffer circuit, the second and fifth transistors are first turned on, to bring the first and second input circuits into the operating state and then, to bring the flip-flop circuit into the operating state. Thereafter, the third and sixth transistors are turned off, to bring the first and second input circuits into the non-operating state.

摘要翻译： 地址缓冲电路包括具有第一和第二输入节点并连接在电源电位和地电位之间的触发器电路。 此外，第一，第二和第三晶体管从第一输入节点和地电位之间的接地侧依次串联连接，以构成第一输入电路，第四，第五和第六晶体管串联连接 从第二输入节点和地电位之间的接地侧起按顺序构成第二输入电路。 外部地址信号被施加到第一晶体管的控制端，并且参考电位被施加到第四晶体管的控制端。 在操作地址缓冲器电路时，首先将第二和第五晶体管导通，以使第一和第二输入电路进入工作状态，然后使触发器电路进入工作状态。 此后，关断第三和第六晶体管，以使第一和第二输入电路处于非工作状态。

公开(公告)号：US5065365A

公开(公告)日：1991-11-12

申请号：US663787

申请日：1991-03-04

申请人： Kazutoshi Hirayama

发明人： Kazutoshi Hirayama

IPC分类号： G11C11/401 ,  G11C11/4076 ,  G11C11/4096

CPC分类号： G11C11/4096 ,  G11C11/4076

摘要： A dynamic random access memory, which includes a data input buffer, a data input latch circuit, a data output buffer, and a switching circuit. For example, in an operation in a read-write cycle, at first, a data signal to be written is stored in the latch circuit 7 concurrent with inputting of an address signal in response to a signal WE. A data signal read from a memory cell is output via the output buffer in response to a signal OE. The switching circuit is turned on, and the data signal which has been latched is provided to the memory cell via a pair of I/O lines. As a result, the time required for the operation in the read-write cycle is shortened.

摘要翻译： 动态随机存取存储器，其包括数据输入缓冲器，数据输入锁存电路，数据输出缓冲器和切换电路。 例如，在读 - 写周期的操作中，首先，响应于信号＆上行＆amp; W的输入地址信号，与写入的数据信号同时存储在锁存电路7中。 存储单元响应于信号＆upbar＆O而经由输出缓冲器输出。开关电路导通，并且已锁存的数据信号经由一对I / O线提供给存储单元。 结果，读写周期中的操作所需的时间缩短。