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15 条记录 (耗时 0.014 秒)

    Internal voltage generating circuit, semiconductor memory device, and method of measuring current consumption, capable of measuring current consumption without cutting wire
    5.
    发明授权
    Internal voltage generating circuit, semiconductor memory device, and method of measuring current consumption, capable of measuring current consumption without cutting wire 失效
    内部电压发生电路，半导体存储器件和测量电流消耗的方法，能够在不切割电线的情况下测量电流消耗

    公开(公告)号：US5835434A

    公开(公告)日：1998-11-10

    申请号：US587684

    申请日：1996-01-17

    申请人： Kazutoshi Hirayama

    发明人： Kazutoshi Hirayama

    IPC分类号： G11C11/407 ,  G05F3/24 ,  G11C5/14 ,  G11C11/401 ,  G11C29/02 ,  G11C29/46 ,  G11C29/50

    CPC分类号： G11C29/021 ,  G11C29/02 ,  G11C29/46 ,  G11C29/50 ,  G11C5/146 ,  G11C11/401 ,  G11C2029/5006

    摘要： This substrate voltage generating circuit (internal voltage generating circuit) includes an oscillator, a p channel transistor, an AND circuit, and a pump circuit. The substrate voltage generating circuit is stopped by applying stop signals S and S to the p channel transistor and the AND circuit connected to the oscillator, and by cutting supply of power supply voltage to the oscillator and a path of output of the oscillator. In order to find current consumption at stand-by of a semiconductor memory device, current consumptions of the whole semiconductor memory device at stand-by before and after operation of the substrate voltage generating circuit is stopped as described above are measured, and the difference between them is calculated. Current consumption of the substrate voltage generating circuit is thus found. As described above, the internal voltage generating circuit can be stopped without cutting a wire, thereby allowing measurement of current consumption of the internal voltage generating circuit at stand-by of the semiconductor memory device. As a result, a problem caused by cutting of the wire can be prevented.

    摘要翻译： 该衬底电压产生电路（内部电压产生电路）包括振荡器，p沟道晶体管，AND电路和泵电路。 通过向p沟道晶体管施加停止信号S和+ E，ovs S + EE以及连接到振荡器的AND电路，并通过切断对振荡器的电源电压和输出路径来停止衬底电压产生电路 的振荡器。 为了在半导体存储器件的待机中寻找电流消耗，如上所述测量基板电压产生电路的操作之前和之后待机的整个半导体存储器件的电流消耗被停止，并且 他们是计算的。 因此发现了基板电压产生电路的电流消耗。 如上所述，可以停止内部电压产生电路而不切断线，从而允许在半导体存储器件待机时测量内部电压产生电路的电流消耗。 结果，可以防止由切割线引起的问题。

    Semiconductor memory device comprising two kinds of memory cells operating in different access speeds and methods of operating and manufacturing the same
    6.
    发明授权
    Semiconductor memory device comprising two kinds of memory cells operating in different access speeds and methods of operating and manufacturing the same 失效
    半导体存储器件包括以不同访问速度操作的两种存储器单元及其操作和制造方法

    公开(公告)号：US5663905A

    公开(公告)日：1997-09-02

    申请号：US469161

    申请日：1995-06-06

    申请人： Ryuichi Matsuo ,  Tomohisa Wada ,  Kazutoshi Hirayama ,  Shigeki Ohbayashi

    发明人： Ryuichi Matsuo ,  Tomohisa Wada ,  Kazutoshi Hirayama ,  Shigeki Ohbayashi

    IPC分类号： G11C11/41 ,  G11C11/00 ,  G11C11/401 ,  H01L27/10 ,  H01L27/105 ,  G11C11/24

    CPC分类号： H01L27/105 ,  G11C11/005

    摘要： A semiconductor memory device comprises a dynamic memory cell array, a static memory cell array, a plurality of word lines, a plurality of DRAM bit line pairs and a plurality of SRAM bit line pairs. The dynamic memory cell array comprises a plurality of dynamic memory cells arranged in the shape of a matrix. The static memory cell array is arranged adjacent to the dynamic memory cell array. The static memory cell array includes the static memory cells arranged in the shape of a matrix. A plurality of word lines are arranged in a plurality of rows. Each word line is connected to the dynamic and static memory cells arranged in the corresponding rows. A plurality of DRAM bit line pairs are arranged in a plurality of columns. Each DRAM bit line pair is connected to the dynamic memory cells. A plurality of SRAM bit line pairs are arranged in the other plurality of columns. Each SRAM bit line pair is connected to the static memory cells arranged in the corresponding columns.

    摘要翻译： 半导体存储器件包括动态存储单元阵列，静态存储单元阵列，多个字线，多个DRAM位线对和多个SRAM位线对。 动态存储单元阵列包括以矩阵形状排列的多个动态存储单元。 静态存储单元阵列被布置成与动态存储单元阵列相邻。 静态存储单元阵列包括以矩阵形状排列的静态存储单元。 多个字线被布置成多行。 每个字线连接到布置在相应行中的动态和静态存储单元。 多个DRAM位线对排列成多列。 每个DRAM位线对连接到动态存储单元。 在其他多个列中布置有多个SRAM位线对。 每个SRAM位线对连接到布置在相应列中的静态存储单元。

    Semiconductor memory device including programmable mode selection circuitry
    7.
    发明授权
    Semiconductor memory device including programmable mode selection circuitry 失效
    半导体存储器件包括可编程模式选择电路

    公开(公告)号：US4833650A

    公开(公告)日：1989-05-23

    申请号：US34094

    申请日：1987-04-02

    申请人： Kazutoshi Hirayama ,  Hideyuki Ozaki ,  Kazuyasu Fujishima ,  Hideto Hidaka

    发明人： Kazutoshi Hirayama ,  Hideyuki Ozaki ,  Kazuyasu Fujishima ,  Hideto Hidaka

    IPC分类号： G11C11/401 ,  G11C7/10 ,  G11C7/22 ,  G11C11/4096

    CPC分类号： G11C7/22 ,  G11C11/4096 ,  G11C7/1033 ,  G11C7/1045

    摘要： A semiconductor memory device includes a plurality of operation mode control circuits provided on a memory chip of the device for respectively executing a corresponding plurality of writing/reading operation modes including at least a static column mode, a high speed page mode and a nibble mode, and a plurality of operation mode selection circuits provided on the memory chip, each of the operation mode selection circuits having a fuse element and a bonding pad for selecting one of the plurality of the operation mode control circuits when the fuse element is cut off or the bonding pad is selectively wired, so that various functions can be selectively effected on the same chip.

    摘要翻译： 半导体存储器件包括设置在该器件的存储器芯片上的多个操作模式控制电路，用于分别执行至少包括静态列模式，高速页模式和半字节模式的对应多个写/读操作模式， 以及设置在所述存储芯片上的多个操作模式选择电路，每个所述操作模式选择电路具有熔丝元件和用于在所述熔丝元件被切断时选择所述多个所述操作模式控制电路中的一个的焊盘， 接合焊盘是有选择地布线的，从而可以在同一芯片上选择性地实现各种功能。

    Semiconductor memory device with a rapid packet data input, capable of operation check with low speed tester
    8.
    发明授权
    Semiconductor memory device with a rapid packet data input, capable of operation check with low speed tester 失效
    具有快速分组数据输入的半导体存储器件，能够与低速测试仪进行运行检查

    公开(公告)号：US06301190B1

    公开(公告)日：2001-10-09

    申请号：US09606413

    申请日：2000-06-29

    申请人： Mitsunori Tsujino ,  Kazutoshi Hirayama ,  Kyoji Yamasaki

    发明人： Mitsunori Tsujino ,  Kazutoshi Hirayama ,  Kyoji Yamasaki

    IPC分类号： G11C800

    CPC分类号： G11C29/48

    摘要： A semiconductor memory device uses in a test mode a clock signal from a tester to allow a test clock conversion circuit and a DLL circuit to generate a rapid internal clock. The internal clock is applied to serial parallel conversion circuits subjecting received, packetized data to serial parallel conversion, and an interface circuit receiving and decoding outputs from the serial-parallel conversion circuits and outputting a command such as ACT to a DRAM core. Furthermore, an internal packet generation circuit uses the internal clock to rapidly generate a testing packet signal. Thus the device's operation can be checked with a low speed tester, without externally receiving a rapid packet signal.

    摘要翻译： 半导体存储器件在测试模式中使用来自测试器的时钟信号，以允许测试时钟转换电路和DLL电路产生快速的内部时钟。 将内部时钟应用于串行并行转换电路，其对接收的分组化数据进行串行并行转换，以及接口电路，从串行/并行转换电路接收和解码输出，并将诸如ACT的命令输出到DRAM内核。 此外，内部分组产生电路使用内部时钟来快速生成测试分组信号。 因此，可以用低速测试仪检查设备的操作，而无需外部接收快速分组信号。

    Semiconductor memory device having redundant circuit and method of testing to see whether or not redundant circuit is used therein
    9.
    发明授权
    Semiconductor memory device having redundant circuit and method of testing to see whether or not redundant circuit is used therein 失效
    具有冗余电路的半导体存储器件和测试方法，以查看其中是否使用冗余电路

    公开(公告)号：US5343429A

    公开(公告)日：1994-08-30

    申请号：US919415

    申请日：1992-07-27

    申请人： Akio Nakayama ,  Kazutoshi Hirayama

    发明人： Akio Nakayama ,  Kazutoshi Hirayama

    IPC分类号： G11C29/00 ,  G11C7/00

    CPC分类号： G11C29/835

    摘要： In a semiconductor memory device having a spare memory cell array and a spare column decoder and a spare row decoder as redundant circuits, redundancy detecting circuits for testing to see whether the redundant circuits are used or not after completion of the semiconductor memory device as a product are set so as to be capable of providing particular current signals or voltage signals, which indicate that the redundant circuits are used to predetermined external terminals, in response to an output signal at a predetermined logic level from a spare row decoder activating circuit or a spare column decoder activating circuit. When an external address signal is supplied to the semiconductor memory device, a signal at a logic level according to whether the redundant circuits are used or not is automatically latched in the redundancy detecting circuits in response to an output signal of the spare row decoder activating circuit or the spare column decoder activating circuit, so that it becomes unnecessary to set the state of electric connection in the redundancy detecting circuits according to whether the redundant circuits are used or not in manufacture.

    摘要翻译： 在具有备用存储单元阵列和备用列解码器和备用行解码器作为冗余电路的半导体存储器件中，冗余检测电路用于在半导体存储器件完成后测试是否使用冗余电路作为产品 被设置为能够响应于来自备用行解码器激活电路或备用电路的预定逻辑电平的输出信号，提供指示将冗余电路用于预定外部端子的特定电流信号或电压信号 列解码器激活电路。 当向半导体存储器件提供外部地址信号时，响应于备用行解码器激活电路的输出信号，自动锁存冗余检测电路中根据冗余电路是否使用逻辑电平的信号 或备用列解码器激活电路，使得根据在制造中是否使用冗余电路，不需要在冗余检测电路中设置电连接的状态。

    Input circuit for logic circuit having node and operating method therefor
    10.
    发明授权
    Input circuit for logic circuit having node and operating method therefor 失效
    具有节点和其操作方法的逻辑电路的输入电路

    公开(公告)号：US5111078A

    公开(公告)日：1992-05-05

    申请号：US758704

    申请日：1991-09-09

    申请人： Hiroshi Miyamoto ,  Kazutoshi Hirayama

    发明人： Hiroshi Miyamoto ,  Kazutoshi Hirayama

    IPC分类号： G11C11/413 ,  G11C8/06 ,  G11C8/18 ,  G11C11/408 ,  H03K3/356 ,  H03K19/0185

    CPC分类号： G11C8/06 ,  G11C8/18 ,  H03K3/356104

    摘要： An address buffer circuit comprises a flip-flop circuit having first and second input nodes and connected between a power-supply potential and a ground potential. In addition, first, second and third transistors are connected in series in that order from the side of the ground between the first input node and the ground potential, to constitute a first input circuit, and fourth, fifth and sixth transistors are connected in series in that order from the side of the ground between the second input node and the ground potential, to constitute a second input circuit. An external address signal is applied to a control terminal of the first transistor, and a reference potential is applied to a control terminal of the fourth transistor. At the time of operating the address buffer circuit, the second and fifth transistors are first turned on, to bring the first and second input circuits into the operating state and then, to bring the flip-flop circuit into the operating state. Thereafter, the third and sixth transistors are turned off, to bring the first and second input circuits into the non-operating state.

    摘要翻译： 地址缓冲电路包括具有第一和第二输入节点并连接在电源电位和地电位之间的触发器电路。 此外，第一，第二和第三晶体管从第一输入节点和地电位之间的接地侧依次串联连接，以构成第一输入电路，第四，第五和第六晶体管串联连接 从第二输入节点和地电位之间的接地侧起按顺序构成第二输入电路。 外部地址信号被施加到第一晶体管的控制端，并且参考电位被施加到第四晶体管的控制端。 在操作地址缓冲器电路时，首先将第二和第五晶体管导通，以使第一和第二输入电路进入工作状态，然后使触发器电路进入工作状态。 此后，关断第三和第六晶体管，以使第一和第二输入电路处于非工作状态。