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公开(公告)号：US20070101237A1
公开(公告)日：2007-05-03
申请号：US11504016
申请日：2006-08-15
IPC分类号： G11C29/00
CPC分类号： G11C29/76 , G06F11/1068 , G06F13/1673 , G11C5/04 , G11C29/72 , G11C2029/0409
摘要： A memory card has a plurality of non-volatile memories and a main controller for controlling the operation of the non-volatile memories. The main controller performs an access control to the non-volatile memories in response to an external access instruction, and an alternate control for alternating an access error-related storage area of the non-volatile memory with other storage area. In the access control, the speeding up of the data transfer between flash memories is achieved by causing the plurality of non-volatile memories to parallel access operate. In the alternation control, the storage areas is made alternative for each non-volatile memory in which an access error occurs.
摘要翻译： 存储卡具有多个非易失性存储器和用于控制非易失性存储器的操作的主控制器。 主控制器响应于外部访问指令对非易失性存储器执行访问控制，以及用于将非易失性存储器的访问错误相关存储区域与其他存储区域交替的替代控制。 在访问控制中，通过使多个非易失性存储器并行访问操作来实现闪速存储器之间的数据传输的加速。 在交替控制中，对于发生访问错误的每个非易失性存储器，存储区域被替代。
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公开(公告)号：US08042021B2
公开(公告)日：2011-10-18
申请号：US13089310
申请日：2011-04-18
CPC分类号： G11C29/76 , G06F11/1068 , G06F13/1673 , G11C5/04 , G11C29/72 , G11C2029/0409
摘要： A memory card has a plurality of non-volatile memories and a main controller for controlling the operation of the non-volatile memories. The main controller performs an access control to the non-volatile memories in response to an external access instruction, and an alternate control for alternating an access error-related storage area of the non-volatile memory with other storage area. In the access control, the speeding up of the data transfer between flash memories is achieved by causing the plurality of non-volatile memories to parallel access operate. In the alternation control, the storage areas is made alternative for each non-volatile memory in which an access error occurs.
摘要翻译： 存储卡具有多个非易失性存储器和用于控制非易失性存储器的操作的主控制器。 主控制器响应于外部访问指令对非易失性存储器执行访问控制，以及用于将非易失性存储器的访问错误相关存储区域与其他存储区域交替的替代控制。 在访问控制中，通过使多个非易失性存储器并行访问操作来实现闪速存储器之间的数据传输的加速。 在交替控制中，对于发生访问错误的每个非易失性存储器，存储区域被替代。
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公开(公告)号：US07954039B2
公开(公告)日：2011-05-31
申请号：US11861190
申请日：2007-09-25
CPC分类号： G11C29/76 , G06F11/1068 , G06F13/1673 , G11C5/04 , G11C29/72 , G11C2029/0409
摘要： A memory card has a plurality of non-volatile memories and a main controller for controlling the operation of the non-volatile memories. The main controller performs an access control to the non-volatile memories in response to an external access instruction, and an alternate control for alternating an access error-related storage area of the non-volatile memory with other storage area. In the access control, the speeding up of the data transfer between flash memories is achieved by causing the plurality of non-volatile memories to parallel access operate. In the alternation control, the storage areas is made alternative for each non-volatile memory in which an access error occurs.
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公开(公告)号：US07290198B2
公开(公告)日：2007-10-30
申请号：US11504016
申请日：2006-08-15
CPC分类号： G11C29/76 , G06F11/1068 , G06F13/1673 , G11C5/04 , G11C29/72 , G11C2029/0409
摘要： A memory card has a plurality of non-volatile memories and a main controller for controlling the operation of the non-volatile memories. The main controller performs an access control to the non-volatile memories in response to an external access instruction, and an alternate control for alternating an access error-related storage area of the non-volatile memory with other storage area. In the access control, the speeding up of the data transfer between flash memories is achieved by causing the plurality of non-volatile memories to parallel access operate. In the alternation control, the storage areas is made alternative for each non-volatile memory in which an access error occurs.
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公开(公告)号：US20110197108A1
公开(公告)日：2011-08-11
申请号：US13089310
申请日：2011-04-18
IPC分类号： G06F11/08
CPC分类号： G11C29/76 , G06F11/1068 , G06F13/1673 , G11C5/04 , G11C29/72 , G11C2029/0409
摘要： A memory card has a plurality of non-volatile memories and a main controller for controlling the operation of the non-volatile memories. The main controller performs an access control to the non-volatile memories in response to an external access instruction, and an alternate control for alternating an access error-related storage area of the non-volatile memory with other storage area. In the access control, the speeding up of the data transfer between flash memories is achieved by causing the plurality of non-volatile memories to parallel access operate. In the alternation control, the storage areas is made alternative for each non-volatile memory in which an access error occurs.
摘要翻译： 存储卡具有多个非易失性存储器和用于控制非易失性存储器的操作的主控制器。 主控制器响应于外部访问指令对非易失性存储器执行访问控制，以及用于将非易失性存储器的访问错误相关存储区域与其他存储区域交替的替代控制。 在访问控制中，通过使多个非易失性存储器并行访问操作来实现闪速存储器之间的数据传输的加速。 在交替控制中，对于发生访问错误的每个非易失性存储器，存储区域被替代。
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公开(公告)号：US20100054069A1
公开(公告)日：2010-03-04
申请号：US12251444
申请日：2008-10-14
IPC分类号： G11C7/00
CPC分类号： G06F12/0246 , G06F13/161 , G06F13/1673 , G06F2212/7206 , G11C7/1006
摘要： The present invention provides a memory system which contributes to improvement in efficiency of a data process accompanying a memory access. A memory system has a rewritable nonvolatile memory, a buffer memory, and a controller. The controller controls, in response to an access request from an external apparatus, first data transfer between the controller and the external apparatus, second data transfer between the controller and the nonvolatile memory, and third data transfer between the controller and the buffer memory, controls transfer from the controller to the buffer memory in the third data transfer and transfer from the buffer memory to the controller in a time sharing manner, and enables the first data transfer or the second data transfer to be performed in parallel with the transfer carried out in the time sharing manner.
摘要翻译： 本发明提供了一种有助于提高伴随存储器访问的数据处理的效率的存储器系统。 存储器系统具有可重写非易失性存储器，缓冲存储器和控制器。 控制器响应于来自外部设备的访问请求控制控制器和外部设备之间的第一数据传输，控制器和非易失性存储器之间的第二数据传输以及控制器和缓冲存储器之间的第三数据传送，控制 在第三次数据传送中从控制器传送到缓冲存储器，并以时间共享的方式从缓冲存储器传输到控制器，并且能够与第一次数据传送或第二数据传输并行执行 时间分享的方式。
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17.发明授权Memory system comprising a controller managing independent data transfer between input-output terminal, synchronous dynamic random access memory, and flash memory 有权存储器系统包括控制输入输出端子，同步动态随机存取存储器和闪存之间的独立数据传输的控制器公开(公告)号：US07450457B2
公开(公告)日：2008-11-11
申请号：US11785177
申请日：2007-04-16
IPC分类号： G11C7/00
CPC分类号： G06F12/0246 , G06F13/161 , G06F13/1673 , G06F2212/7206 , G11C7/1006
摘要： A memory system contributes to improvement in efficiency of a data process accompanying a memory access. The memory system has a rewritable nonvolatile memory, a buffer memory, and a controller. The controller controls, in response to an access request from an external apparatus, first data transfer between the controller and the external apparatus, second data transfer between the controller and the nonvolatile memory, and third data transfer between the controller and the buffer memory, controls transfer from the controller to the buffer memory in the third data transfer and transfer from the buffer memory to the controller in a time sharing manner, and enables the first data transfer or the second data transfer to be performed in parallel with the transfer carried out in the time sharing manner.
摘要翻译： 存储器系统有助于提高伴随存储器访问的数据处理的效率。 存储器系统具有可重写的非易失性存储器，缓冲存储器和控制器。 控制器响应于来自外部设备的访问请求控制控制器和外部设备之间的第一数据传输，控制器和非易失性存储器之间的第二数据传输以及控制器和缓冲存储器之间的第三数据传送，控制 在第三次数据传送中从控制器传送到缓冲存储器，并以时间共享的方式从缓冲存储器传输到控制器，并且能够与第一次数据传送或第二数据传输并行执行 时间分享的方式。
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公开(公告)号：US20070285997A1
公开(公告)日：2007-12-13
申请号：US11785177
申请日：2007-04-16
IPC分类号： G11C11/34
CPC分类号： G06F12/0246 , G06F13/161 , G06F13/1673 , G06F2212/7206 , G11C7/1006
摘要： The present invention provides a memory system which contributes to improvement in efficiency of a data process accompanying a memory access. A memory system has a rewritable nonvolatile memory, a buffer memory, and a controller. The controller controls, in response to an access request from an external apparatus, first data transfer between the controller and the external apparatus, second data transfer between the controller and the nonvolatile memory, and third data transfer between the controller and the buffer memory, controls transfer from the controller to the buffer memory in the third data transfer and transfer from the buffer memory to the controller in a time sharing manner, and enables the first data transfer or the second data transfer to be performed in parallel with the transfer carried out in the time sharing manner.
摘要翻译： 本发明提供了一种有助于提高伴随存储器访问的数据处理的效率的存储器系统。 存储器系统具有可重写非易失性存储器，缓冲存储器和控制器。 控制器响应于来自外部设备的访问请求控制控制器和外部设备之间的第一数据传输，控制器和非易失性存储器之间的第二数据传输以及控制器和缓冲存储器之间的第三数据传送，控制 在第三次数据传送中从控制器传送到缓冲存储器，并以时间共享的方式从缓冲存储器传输到控制器，并且能够与第一次数据传送或第二数据传输并行执行 时间分享的方式。
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公开(公告)号：US20060036804A1
公开(公告)日：2006-02-16
申请号：US11246074
申请日：2005-10-11
IPC分类号： G06F12/00
CPC分类号： G06F21/79 , G06F12/1425
摘要： To prevent stored information from being changed even at the occurrence of an abnormal condition in an upstream side of a system due to uncontrollable run of an OS. A nonvolatile storage means having data storage areas and management areas for them in units of predetermined physical addresses has an access protect definition table TLB in a predetermined physical address, and the table has access attribute information defining whether to permit or not access to the data storage areas in association with the physical addresses. The memory system itself possesses access attribute information defining whether to permit or not a write to and a read from the data storage areas in association with addresses to implement an access protect function for write and read. Therefore, the access protect function is maintained even if an abnormal condition occurs in a host device that manages the memory system or controls it as a peripheral circuit.
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公开(公告)号：US20050162929A1
公开(公告)日：2005-07-28
申请号：US11082859
申请日：2005-03-18
CPC分类号： G06F12/0246 , G06F13/161 , G06F13/1673 , G06F2212/7206 , G11C7/1006
摘要： The present invention provides a memory system which contributes to improvement in efficiency of a data process accompanying a memory access. A memory system has a rewritable nonvolatile memory, a buffer memory, and a controller. The controller controls, in response to an access request from an external apparatus, first data transfer between the controller and the external apparatus, second data transfer between the controller and the nonvolatile memory, and third data transfer between the controller and the buffer memory, controls transfer from the controller to the buffer memory in the third data transfer and transfer from the buffer memory to the controller in a time sharing manner, and enables the first data transfer or the second data transfer to be performed in parallel with the transfer carried out in the time sharing manner.
摘要翻译： 本发明提供了一种有助于提高伴随存储器访问的数据处理的效率的存储器系统。 存储器系统具有可重写非易失性存储器，缓冲存储器和控制器。 控制器响应于来自外部设备的访问请求控制控制器和外部设备之间的第一数据传输，控制器和非易失性存储器之间的第二数据传输以及控制器和缓冲存储器之间的第三数据传送，控制 在第三次数据传送中从控制器传送到缓冲存储器，并以时间共享的方式从缓冲存储器传输到控制器，并且能够与第一次数据传送或第二数据传输并行执行 时间分享的方式。
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