公开(公告)号：US20240152288A1

公开(公告)日：2024-05-09

申请号：US18412635

申请日：2024-01-15

Applicant: Silicon Motion, Inc.

Inventor： Tsung-Chieh Yang ,  Chun-Chieh Kuo ,  Ching-Hui Lin ,  Yang-Chih Shen

IPC: G06F3/06 ,  G06F12/02 ,  G11C11/56

CPC classification number: G06F3/0634 ,  G06F3/0604 ,  G06F3/064 ,  G06F3/0679 ,  G06F12/0246 ,  G11C11/5628 ,  G11C11/5642 ,  G06F2212/7201 ,  G06F2212/7206 ,  Y02D10/00

Abstract: A flash memory controller for controlling a flash memory module includes a communication interface for receiving a first data and a second data; and a processing circuit for dynamically controlling a data writing mode of the flash memory module according to an amount of stored data in the flash memory module. If the amount of stored data in the flash memory module is less than a first threshold when the communication interface receives the first data, the processing circuit controls the flash memory module so that the first data is written into the first data block under an one-bit-per-cell mode. If the amount of stored data in the flash memory module is greater than the first threshold when the communication interface receives the second data, the processing circuit controls the flash memory module so that the second data is written into the second data block under a two-bit-per-cell mode.

公开(公告)号：US20230325079A1

公开(公告)日：2023-10-12

申请号：US18336316

申请日：2023-06-16

Applicant: Silicon Motion, Inc.

Inventor： Te-Kai WANG ,  Yu-Da CHEN

IPC: G06F3/06 ,  G06F12/02 ,  G11C16/22 ,  G11C16/10 ,  G11C16/26

CPC classification number: G06F3/0605 ,  G06F3/0634 ,  G06F3/0619 ,  G06F3/0679 ,  G06F12/0246 ,  G11C16/22 ,  G11C16/10 ,  G11C16/26 ,  G06F2212/7206 ,  G06F2212/72 ,  G06F2212/7207 ,  G06F2212/7209

Abstract: A data storage device with flash memory. The controller receives a mode selection command from a host. In response to the mode selection command, the controller sends a ready-to-transfer message to the host, to further receive a data out message from the host that is sent by the host in response to the ready-to-transfer message. The ready-to-transfer message and the data out message are UFS protocol information unit (UPIU) messages. The data out message is arranged to rewrite a first mode page setting among a plurality of mode page settings of firmware stored in the flash memory. In response to the data out message, the controller determines whether the data out message will change mode parameters which cannot be rewritten in the first mode page setting, to adopt or refuse new mode parameters issued through the data out message for the first mode page setting.

公开(公告)号：US11652884B2

公开(公告)日：2023-05-16

申请号：US17351864

申请日：2021-06-18

Applicant: Pure Storage, Inc.

Inventor： Taras Glek

IPC: G06F12/00 ,  H04L67/1097 ,  G06F3/06 ,  G11C29/52 ,  G06F12/02 ,  H04L49/10 ,  G06F11/20 ,  G06F11/10 ,  H03M13/15 ,  H04L67/51

CPC classification number: H04L67/1097 ,  G06F3/06 ,  G06F3/061 ,  G06F3/0604 ,  G06F3/065 ,  G06F3/067 ,  G06F3/0611 ,  G06F3/0613 ,  G06F3/0635 ,  G06F3/0655 ,  G06F3/0659 ,  G06F3/0685 ,  G06F3/0688 ,  G06F3/0689 ,  G06F11/1068 ,  G06F11/2092 ,  G06F12/0246 ,  G11C29/52 ,  H03M13/154 ,  H04L49/10 ,  H04L67/51 ,  G06F11/108 ,  G06F2201/805 ,  G06F2201/845 ,  G06F2212/7206 ,  G06F2212/7207

Abstract: A storage system determines source addresses, and destination addresses in a storage system, for network traffic. The storage system determines a hash algorithm, from a plurality of hash algorithms. The hash algorithm is to be used across the source addresses for load-balancing the network traffic to the destination addresses. The storage system determines that the hash algorithm more closely meets one or more load-balancing criteria than at least one other hash algorithm, of the plurality of hash algorithms. The storage system distributes the network traffic from the source addresses to the destination addresses in the storage system, with load-balancing according to the determined hash algorithm.

公开(公告)号：US20190012484A1

公开(公告)日：2019-01-10

申请号：US15748893

申请日：2016-08-25

Applicant: Apple Inc.

Inventor： Manu Gulati ,  Joseph Sokol, Jr. ,  Jeffrey R. Wilcox ,  Bernard J. Semeria ,  Michael J. Smith

IPC: G06F21/72 ,  G06F21/78 ,  G06F12/14 ,  G06F12/1027 ,  G06F12/02 ,  H04L9/08

CPC classification number: G06F21/72 ,  G06F12/0246 ,  G06F12/1027 ,  G06F12/1408 ,  G06F21/78 ,  G06F2212/7206 ,  G06F2212/7208 ,  G06F2221/2143 ,  H04L9/0861 ,  H04L9/0894 ,  H04L2209/12

Abstract: In one embodiment, a system includes a non-volatile memory that may serve as both the main memory system and the backing store (or persistent storage). In some embodiments, the non-volatile memory is divided into a main memory portion and a persistent portion. Data in the main memory operation may be encrypted using one or more first keys, and data in the persistent portion may be encrypted using one or more second keys, in an embodiment. The volatile behavior of main memory may be implemented by discarding the one or more first keys in a power down event or other event that indicates a loss of main memory data, while the one or more second keys may be retained. In one embodiment, the physical address space of the non-volatile memory may be a mapping from a second physical address space that is used within the system.

公开(公告)号：US10083078B2

公开(公告)日：2018-09-25

申请号：US15282577

申请日：2016-09-30

Applicant: Micron Technology, Inc.

Inventor： Wanmo Wong

IPC: G06F12/02 ,  G06F11/10 ,  G06F3/06 ,  H03M13/11 ,  H03M13/15

CPC classification number: G06F11/1044 ,  G06F3/0604 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/065 ,  G06F3/0652 ,  G06F3/0659 ,  G06F3/0679 ,  G06F12/02 ,  G06F12/0207 ,  G06F12/0215 ,  G06F12/0246 ,  G06F2212/1044 ,  G06F2212/2022 ,  G06F2212/7204 ,  G06F2212/7206 ,  G11C2211/5641 ,  H03M13/1174 ,  H03M13/152

Abstract: Embodiments for partitioning a non-volatile memory device is described. In one embodiment a memory system includes a first addressable range of memory blocks for storing different types of data. The memory system is partitioned to include a second addressable range of memory blocks capable of storing data indicating attributes of the first addressable range of memory blocks. The second addressable range of memory blocks may also be periodically updated such that the capacities of the first addressable range of memory blocks may be dynamically adjusted depending on application needs and changes to the non-volatile memory device over time In some embodiments, one partition of a memory device may be configured for high reliability data storage while a second partition is configured for normal reliability storage.

公开(公告)号：US10073626B2

公开(公告)日：2018-09-11

申请号：US13838699

申请日：2013-03-15

Applicant: Virident Systems, LLC

Inventor： Vijay Karamcheti ,  Ashish Singhai ,  Shibabrata Mondal ,  Ajith Kumar

IPC: G06F12/00 ,  G06F3/06 ,  G06F12/02 ,  G06F9/48 ,  G06F9/50

CPC classification number: G06F3/061 ,  G06F3/0611 ,  G06F3/0655 ,  G06F3/0659 ,  G06F3/0679 ,  G06F3/0688 ,  G06F9/4881 ,  G06F9/5016 ,  G06F12/0246 ,  G06F2212/7206 ,  G06F2212/7208

Abstract: Some implementations include a method of managing a hosted non-volatile random-access memory (NVRAM) based storage subsystem that includes NVRAM devices. The method includes: receiving, at a device driver on the host computing device, write requests each requesting to write a respective unit of data to the NVRAM-based storage subsystem; categorizing the write requests into subgroups of write requests, where write requests within respective subgroups are mutually exclusive; ascertaining a load condition of each of several of the NVRAM devices of the NVRAM-based storage subsystem; identifying a target location on at least one NVRAM device to service a particular subgroup of write requests according to the ascertained load conditions of the NVRAM devices of the NVRAM-based storage subsystem; and servicing the particular subgroup of write requests by writing the corresponding units of data to the identified target location on the at least one NVRAM device of the NVRAM-based storage subsystem.

公开(公告)号：US10019352B2

公开(公告)日：2018-07-10

申请号：US14333365

申请日：2014-07-16

Applicant: SanDisk Technologies LLC

Inventor： Michael Brown ,  Nisha Talagala ,  Robert Wood ,  Ned Plasson

IPC: G06F12/00 ,  G06F12/02 ,  G06F12/0893 ,  G06F12/0871 ,  G06F12/12 ,  G06F3/06

CPC classification number: G06F12/023 ,  G06F3/0631 ,  G06F3/0679 ,  G06F3/0688 ,  G06F12/0238 ,  G06F12/0871 ,  G06F12/0893 ,  G06F12/12 ,  G06F2212/1024 ,  G06F2212/1044 ,  G06F2212/214 ,  G06F2212/466 ,  G06F2212/604 ,  G06F2212/7204 ,  G06F2212/7205 ,  G06F2212/7206

Abstract: A storage layer may over-provision physical storage resources of a storage medium by reserving a portion of the full physical storage capacity of the storage medium for use as reserve capacity. The reserve capacity may be used to prevent write stall conditions and/or for grooming operations, such as storage recovery, refresh, and the like. A reserve module may be configured to adapt the reserve capacity in accordance with, inter alia, operating conditions on the storage layer. The reserve module may be configured to dynamically modify the storage capacity available through the storage layer. A cache layer configured to cache data of a backing store on the storage layer, may be configured to add and/or remove cache entries in response to changes in the reserve capacity.

公开(公告)号：US10007460B2

公开(公告)日：2018-06-26

申请号：US15643501

申请日：2017-07-07

Applicant: Silicon Motion Inc.

Inventor： Tsung-Chieh Yang ,  Chun-Chieh Kuo ,  Ching-Hui Lin ,  Yang-Chih Shen

IPC: G11C11/34 ,  G11C16/04 ,  G06F3/06 ,  G06F12/02 ,  G11C11/56

CPC classification number: G06F3/0634 ,  G06F3/0604 ,  G06F3/064 ,  G06F3/0679 ,  G06F12/0246 ,  G06F2212/7201 ,  G06F2212/7206 ,  G11C11/5628 ,  G11C11/5642 ,  Y02D10/13

Abstract: A flash memory controller for controlling a flash memory module includes a communication interface for receiving a first data and a second data; and a processing circuit for dynamically controlling a data writing mode of the flash memory module according to an amount of stored data in the flash memory module. If the amount of stored data in the flash memory module is less than a first threshold when the communication interface receives the first data, the processing circuit controls the flash memory module so that the first data is written into the first data block under an one-bit-per-cell mode. If the amount of stored data in the flash memory module is greater than the first threshold when the communication interface receives the second data, the processing circuit controls the flash memory module so that the second data is written into the second data block under a two-bit-per-cell mode.

公开(公告)号：US20180081543A1

公开(公告)日：2018-03-22

申请号：US15269518

申请日：2016-09-19

Applicant: Micron Technology, Inc.

Inventor： Kishore K. Muchherla ,  Ashutosh Malshe ,  Sampath K. Ratnam ,  Peter Feeley ,  Michael G. Miller ,  Christopher S. Hale ,  Renato C. Padilla

IPC: G06F3/06 ,  G06F12/0893

CPC classification number: G06F3/0604 ,  G06F3/064 ,  G06F3/0653 ,  G06F3/0679 ,  G06F11/34 ,  G06F12/0246 ,  G06F12/0888 ,  G06F12/0893 ,  G06F2201/885 ,  G06F2212/1016 ,  G06F2212/1044 ,  G06F2212/222 ,  G06F2212/502 ,  G06F2212/601 ,  G06F2212/7205 ,  G06F2212/7206

Abstract: A memory device having a memory controller is configured to operate a hybrid cache including a dynamic cache including XLC blocks and a static cache including the SLC blocks. The memory controller is configured to disable at least one of the static cache or the dynamic cache. A method of operating a memory device includes partitioning a memory array into a first portion of SLC blocks and a second portion of XLC blocks, storing at least a portion of host data into the first portion of SLC blocks as a static cache; and storing at least another portion of the host data into the second portion of XLC blocks in an SLC mode as a dynamic cache responsive to a burst of host data being determined to be greater than the static cache can handle. Additional memory devices, methods, and computer systems are also described.

公开(公告)号：US09811461B1

公开(公告)日：2017-11-07

申请号：US14690370

申请日：2015-04-17

Applicant: Marvin Dela Cruz Fenol ,  Jik-Jik Oyong Abad ,  Precious Nezaiah Umali Pestano

Inventor： Marvin Dela Cruz Fenol ,  Jik-Jik Oyong Abad ,  Precious Nezaiah Umali Pestano

IPC: G06F12/02 ,  G06F12/0831

CPC classification number: G06F12/0246 ,  G06F2212/7201 ,  G06F2212/7202 ,  G06F2212/7203 ,  G06F2212/7204 ,  G06F2212/7206 ,  G06F2212/7207 ,  G06F2212/7209

Abstract: In an embodiment of the invention, a method comprises: requesting an update or modification on a control data in at least one flash block in a storage memory; requesting a cache memory; replicating, from the storage memory to the cache memory, the control data to be updated or to be modified; moving a clean cache link list to a dirty cache link list so that the dirty cache link list is changed to reflect the update or modification on the control data; and moving the dirty cache link list to a for flush link list and writing an updated control data from the for flush link list to a free flash page in the storage memory.