公开(公告)号：US06888399B2

公开(公告)日：2005-05-03

申请号：US10358491

申请日：2003-02-04

申请人： Michio Nakagawa ,  Kazuo Sato ,  Hiromi Uenoyama ,  Yasuyuki Ohnishi ,  Kazunori Torii

发明人： Michio Nakagawa ,  Kazuo Sato ,  Hiromi Uenoyama ,  Yasuyuki Ohnishi ,  Kazunori Torii

IPC分类号： G05F1/46 ,  G05F1/10 ,  G05F3/02

CPC分类号： G11C5/145 ,  G05F1/468 ,  H01L27/0222 ,  H01L29/94

摘要： A semiconductor device is equipped with a step-up circuit having a series of multiple charge pump units. Each of the units has a well separation type MOS transistor. The separation well of the transistor is coupled to a high potential so as to form double reverse biases between the N-type well and a P-type substrate and between the N-type well and a P-type well. This permits the threshold Vth of the MOS transistor to be held at low level. The units are provided with a clock whose current supply capability is limited until a predetermined condition (that a predetermined period of time has elapsed after the onset of the step-up circuit by a startup signal or that the output voltage has reached a predetermined level). This limitation of the clock facilitates suppression of power consumption by the step-up circuit during a startup, thereby reducing changes in amplitude of a supply voltage.

公开(公告)号：US06307777B1

公开(公告)日：2001-10-23

申请号：US09646789

申请日：2000-09-21

申请人： Noriaki Katsuhara ,  Yoshihiro Tada ,  Hiromi Uenoyama

发明人： Noriaki Katsuhara ,  Yoshihiro Tada ,  Hiromi Uenoyama

IPC分类号： G11C1604

CPC分类号： G11C29/24 ,  G11C16/0441

摘要： The same information is stored in two memory cells (26 and 26′) and the two memory cells are connected in parallel (OR) at a normal reading to synthesize an electric current in conformity with information in the two memory cells. Even if a floating gate and drain are shorted with each other in a storage transistor in one of the memory cells when a tunnel oxide film is deteriorated, destroyed or shorted by a high-tension stress, the discriminating voltage of a sense amplifier is determined so as to ensure normal reading of information in the other memory cell. The two memory cells are separated at test-reading for independent operations to ensure individual testing each memory cell.

摘要翻译： 相同的信息存储在两个存储单元（26和26'）中，并且两个存储器单元以正常读取并行连接（或），以根据两个存储器单元中的信息合成电流。 即使当隧道氧化膜劣化，被高压应力破坏或短路时，浮动栅极和漏极在存储单元之一的存储晶体管中彼此短路，则读出放大器的识别电压被确定为 以确保其他存储单元中信息的正常读取。 两个存储单元在测试读取时被分离，用于独立操作，以确保对每个存储单元进行单独测试。

公开(公告)号：US5561635A

公开(公告)日：1996-10-01

申请号：US135178

申请日：1993-10-12

申请人： Yoshihiro Tada ,  Hiromi Uenoyama

发明人： Yoshihiro Tada ,  Hiromi Uenoyama

IPC分类号： G11C29/50 ,  G11C29/00

CPC分类号： G11C29/50 ,  G11C17/14

摘要： A sense circuit includes a sense amplifier and a pull-up resistor circuit disposed on the input side of the sense amplifier. In response to a test selection signal, a read voltage applying circuit applies an external voltage to a selected memory cell and the total resistance of the resistor circuit is switched from a normal resistance to a smaller resistance for testing. Since the input side of the sense amplifier is pulled up through the resistor circuit with the resistance for testing, it is possible to detect the storage state of the selected memory cell under a stricter condition.

摘要翻译： 检测电路包括设置在读出放大器的输入侧的读出放大器和上拉电阻电路。 响应于测试选择信号，读取电压施加电路向所选存储单元施加外部电压，并且将电阻电路的总电阻从正常电阻切换到较小的测试电阻。 由于读出放大器的输入侧通过具有用于测试的电阻的电阻电路被上拉，因此可以在更严格的条件下检测所选存储单元的存储状态。

公开(公告)号：US5541873A

公开(公告)日：1996-07-30

申请号：US490816

申请日：1995-06-15

申请人： Kiyoshi Nishimura ,  Hideki Hayashi ,  Jun Muramoto ,  Takaaki Fuchikami ,  Hiromi Uenoyama

发明人： Kiyoshi Nishimura ,  Hideki Hayashi ,  Jun Muramoto ,  Takaaki Fuchikami ,  Hiromi Uenoyama

IPC分类号： G11C14/00 ,  G11C11/22 ,  G11C16/04 ,  G11C17/00 ,  H01L21/8246 ,  H01L21/8247 ,  H01L27/10 ,  H01L27/105 ,  H01L29/788 ,  H01L29/792

CPC分类号： G11C11/22

摘要： A nonvolatile memory having a simple structure where recorded information can be read nondestructively. A voltage is applied between a control gate and a memory gate for writing. A ferroelectric layer is polarized in accordance with the polarization of the applied voltage. A control gate voltage, necessary to form a channel, is small when the ferroelectric layer is polarized with the control gate side negative (polarized with second polarization). The control gate voltage V.sub.cg necessary to form a channel is large when the ferroelectric layer is polarized with the control gate side positive (polarized with first polarization). The reference voltage is applied to the control gate for reading. A large drain current flows when the ferroelectric layer is polarized with the second polarization and a small drain current flows when the ferroelectric layer is polarized with the first polarization. Recorded information can be read by detecting the drain current. The polzarization state of the ferroelectric layer is not affected by the reading operation.

摘要翻译： 具有简单结构的非易失性存储器，其中记录信息可被非破坏性地读取。 在控制栅极和写入存储器栅之间施加电压。 铁电层根据施加的电压的极化而极化。 当铁电层以控制栅极侧为负极化（以第二极化为极化）极化时，形成通道所需的控制栅极电压很小。 当铁电层以控制栅极正极化（以第一极化为极化）极化时，形成沟道所需的控制栅极电压Vcg大。 参考电压施加到控制门进行读取。 当铁电层与第二极化极化时，大的漏极电流流动，而当铁电层以第一极化极化时，漏极电流流过较小。 通过检测漏极电流可以读取记录的信息。 铁电层的极化状态不受读取操作的影响。