公开(公告)号：US20070122964A1

公开(公告)日：2007-05-31

申请号：US11669051

申请日：2007-01-30

申请人： Michio NAKAGAWA ,  Kazuo SATO ,  Hiromi UENOYAMA ,  Yasuyuki OHNISHI ,  Kazunori TORII

发明人： Michio NAKAGAWA ,  Kazuo SATO ,  Hiromi UENOYAMA ,  Yasuyuki OHNISHI ,  Kazunori TORII

IPC分类号： H01L21/8238 ,  H01L29/76

CPC分类号： G11C5/145 ,  G05F1/468 ,  H01L27/0222 ,  H01L29/94

摘要： A semiconductor device is equipped with a step-up circuit having a series of multiple charge pump units. Each of the units has a well separation type MOS transistor. The separation well of the transistor is coupled to a high potential so as to form double reverse biases between the N-type well and a P-type substrate and between the N-type well and a P-type well. This permits the threshold Vth of the MOS transistor to be held at low level. The units are provided with a clock whose current supply capability is limited until a predetermined condition (that a predetermined period of time has elapsed after the onset of the step-up circuit by a startup signal or that the output voltage has reached a predetermined level). This limitation of the clock facilitates suppression of power consumption by the step-up circuit during a startup, thereby reducing changes in amplitude of a supply voltage.

摘要翻译： 半导体器件配备有具有一系列多个电荷泵单元的升压电路。 每个单元具有良好的分离型MOS晶体管。 晶体管的分离阱耦合到高电位，以在N型阱和P型衬底之间以及在N型阱和P型阱之间形成双重反向偏压。 这允许MOS晶体管的阈值Vth保持在低电平。 这些单元设置有时钟，其电流供应能力被限制到预定条件（通过启动信号启动升压电路之后经过了预定时间段或者输出电压已经达到预定水平） 。 时钟的这种限制有助于抑制起动期间升压电路的功耗，从而减小电源电压的幅度变化。

公开(公告)号：US5633821A

公开(公告)日：1997-05-27

申请号：US374221

申请日：1995-01-18

申请人： Kiyoshi Nishimura ,  Hideki Hayashi ,  Jun Muramoto ,  Takaaki Fuchikami ,  Hiromi Uenoyama

发明人： Kiyoshi Nishimura ,  Hideki Hayashi ,  Jun Muramoto ,  Takaaki Fuchikami ,  Hiromi Uenoyama

IPC分类号： G11C14/00 ,  G11C11/22 ,  G11C16/04 ,  G11C17/00 ,  H01L21/8247 ,  H01L27/10 ,  H01L29/788 ,  H01L29/792 ,  H01L29/78

CPC分类号： G11C11/22 ,  G11C11/223

摘要： A nonvolatile memory with a simple structure where recorded information can be read without destruction. A voltage is impressed between a control gate and a memory gate for writing. A ferroelectric layer is polarized in accordance with the direction of the impressed voltage. A control gate voltage to make channel is small when the ferroelectric layer is polarized with the control gate side being positive. Control gate voltage to make channel is large when the ferroelectric layer is polarized with the control gate side being negative. The reference voltage is impressed on the control gate for reading. A large drain current flows when the ferroelectric layer is polarized with a second polarization and a small drain current flows when the ferroelectric layer is polarized with a first polarization. Record information can be read by detecting the drain current. Polarization status of the ferroelectric is not destroyed in the reading operation.

摘要翻译： 具有简单结构的非易失性存储器，可以无损地读取记录信息。 在控制门和用于写入的存储器门之间施加电压。 铁电层根据外加电压的方向极化。 当铁电层在控制栅极侧为正极极化时，使沟道的控制栅极电压较小。 当铁电层在控制栅极侧为负极极化时，控制栅极电压使沟道大。 参考电压施加在控制门上用于读取。 当铁电层以第二偏振极化时，大的漏极电流流动，而当铁电层以第一偏振极化时，小的漏极电流流过。 通过检测漏极电流可以读取记录信息。 在阅读操作中铁电的极化状态不会被破坏。

公开(公告)号：US5592409A

公开(公告)日：1997-01-07

申请号：US374216

申请日：1995-01-18

申请人： Kiyoshi Nishimura ,  Hideki Hayashi ,  Jun Muramoto ,  Takaaki Fuchikami ,  Hiromi Uenoyama

发明人： Kiyoshi Nishimura ,  Hideki Hayashi ,  Jun Muramoto ,  Takaaki Fuchikami ,  Hiromi Uenoyama

IPC分类号： G11C14/00 ,  G11C11/22 ,  G11C16/04 ,  G11C17/00 ,  H01L21/8246 ,  H01L21/8247 ,  H01L27/10 ,  H01L27/105 ,  H01L29/788 ,  H01L29/792

CPC分类号： G11C11/22 ,  G11C11/223

摘要： Nonvolatile memory with a simple structure where recorded information can be read without destruction: Voltage is impressed between control gate CG and memory gate MG at a writing operation. A ferroelectric layer 32 is polarized in accordance with the direction of the impressed voltage. The control gate voltage V.sub.CG to make a channel is low when the ferroelectric layer 32 is polarized with the control gate side being positive (polarized with second status). The control gate voltage V.sub.CG to make a channel is high when the ferroelectric layer 32 is polarized with the control gate side being negative (polarized with the first status). The reference voltage V.sub.ref is impressed to the control gate CG at the reading operation. A high drain current flows when the ferroelectric layer is polarized with the second status and low drain current flows when the ferroelectric layer is polarized with the first status. Recorded information can be read by detecting the drain current. With this reading operation, the polarization status is not destroyed.

摘要翻译： 具有简单结构的非易失性存储器，其中记录的信息可以被读取而不会被破坏：在写入操作时在控制栅极CG和存储器门MG之间施加电压。 铁电层32根据外加电压的方向极化。 当铁电层32被极化而控制栅极侧为正极化（第二状态极化）时，使沟道的控制栅极电压VCG较低。 当铁电层32在控制栅极侧为负极化（以第一状态极化）为极化时，使沟道的控制栅极电压VCG较高。 参考电压Vref在读取操作时被施加到控制栅极CG。 当铁电层以第二状态极化并且当铁电层以第一状态极化时，低漏极电流流动时，高漏极电流流动。 通过检测漏极电流可以读取记录的信息。 通过这种阅读操作，极化状态不会被破坏。

公开(公告)号：US5973357A

公开(公告)日：1999-10-26

申请号：US47121

申请日：1998-03-24

申请人： Hiromi Uenoyama ,  Junichi Hikita

发明人： Hiromi Uenoyama ,  Junichi Hikita

IPC分类号： H01L21/8247 ,  H01L21/8246 ,  H01L27/105 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L29/42324 ,  H01L27/115 ,  H01L29/7883

摘要： A non-volatile memory element, which includes a transistor and stores data by changing its threshold voltage, includes a semiconductor substrate, an electrically chargeable floating gate electrode layer above the main surface of the substrate, another electrically chargeable floating gate electrode layer above the main surface of the substrate, and a control gate electrode layer above these floating gate electrode layers, separated from them by an insulating film such that the voltage of the control gate electrode layer controls charged conditions of the floating gate electrode layers which are insulated from each other and disposed along the direction of the current flow in the transistor.

摘要翻译： 包括晶体管并通过改变其阈值电压来存储数据的非易失性存储元件包括半导体衬底，在衬底的主表面上方的可充电的浮置栅电极层，在主体上方的另一个可充电浮栅电极层 衬底的表面以及这些浮栅电极层之上的控制栅极电极层，通过绝缘膜与它们隔开，使得控制栅电极层的电压控制彼此绝缘的浮栅电极层的充电条件 并且沿着晶体管中的电流流动的方向设置。

公开(公告)号：US5541871A

公开(公告)日：1996-07-30

申请号：US374246

申请日：1995-01-18

申请人： Kiyoshi Nishimura ,  Hideki Hayashi ,  Jun Muramoto ,  Takaaki Fuchikami ,  Hiromi Uenoyama

发明人： Kiyoshi Nishimura ,  Hideki Hayashi ,  Jun Muramoto ,  Takaaki Fuchikami ,  Hiromi Uenoyama

IPC分类号： G11C14/00 ,  G11C11/22 ,  G11C16/04 ,  G11C17/00 ,  H01L21/8246 ,  H01L21/8247 ,  H01L27/10 ,  H01L27/105 ,  H01L29/788 ,  H01L29/792 ,  G11C7/00

CPC分类号： G11C11/22

摘要： Nonvolatile memory with simple structure where recorded information can be read without destroy: Voltage is impressed to control gate CG and channel is grounded at writing operation. Ferroelectric layer 32 is polarized in accordance with whether the applied voltage is larger than threshold voltage of the memory device. Control gate voltage V.sub.CC to make channel is little when the ferro-electric layer 32 is polarized with control gate side being positive (polarized with second status). Control gate voltage V.sub.CG to make channel is large when the ferroelectric layer 32 is polarized with control gate side being negative (polarized with first status). The reference voltage V.sub.ref is impressed to the control gate CG at reading operation. Large drain current flows when the ferroelectric layer is polarized with second status and little drain current flows when the ferroelectric layer is polarized with first status. Recorded information can be read by detecting the drain current. By this reading operation, polarization status is not destroyed.

摘要翻译： 具有简单结构的非易失性存储器，其中记录的信息可以被读取而不破坏：电压被施加到控制栅极CG，并且通道在写入操作时接地。 铁电层32根据所施加的电压是否大于存储器件的阈值电压而极化。 当铁电层32在控制栅极侧为正极化（极化具有第二状态）时，控制栅极电压VCC使沟道很小。 当铁电层32被极化，控制栅极侧为负极化（第一状态极化）时，控制栅极电压VCG使沟道大。 参考电压Vref在读取操作时被施加到控制栅极CG。 当铁电层以第二状态极化时，大的漏极电流流动，当铁电层以第一状态极化时，漏极电流很小。 通过检测漏极电流可以读取记录的信息。 通过这种阅读操作，极化状态不会被破坏。

公开(公告)号：US07190211B2

公开(公告)日：2007-03-13

申请号：US11059255

申请日：2005-02-15

申请人： Michio Nakagawa ,  Kazuo Sato ,  Hiromi Uenoyama ,  Yasuyuki Ohnishi ,  Kazunori Torii

发明人： Michio Nakagawa ,  Kazuo Sato ,  Hiromi Uenoyama ,  Yasuyuki Ohnishi ,  Kazunori Torii

IPC分类号： G05F1/10 ,  G05F3/02

CPC分类号： G11C5/145 ,  G05F1/468 ,  H01L27/0222 ,  H01L29/94

摘要： A semiconductor device is equipped with a step-up circuit having a series of multiple charge pump units. Each of the units has a well separation type MOS transistor. The separation well of the transistor is coupled to a high potential so as to form double reverse biases between the N-type well and a P-type substrate and between the N-type well and a P-type well. This permits the threshold Vth of the MOS transistor to be held at low level. The units are provided with a clock whose current supply capability is limited until a predetermined condition (that a predetermined period of time has elapsed after the onset of the step-up circuit by a startup signal or that the output voltage has reached a predetermined level). This limitation of the clock facilitates suppression of power consumption by the step-up circuit during a startup, thereby reducing changes in amplitude of a supply voltage.

摘要翻译： 半导体器件配备有具有一系列多个电荷泵单元的升压电路。 每个单元具有良好的分离型MOS晶体管。 晶体管的分离阱耦合到高电位，以在N型阱和P型衬底之间以及在N型阱和P型阱之间形成双重反向偏压。 这允许MOS晶体管的阈值Vth保持在低电平。 这些单元设置有时钟，其电流供应能力被限制到预定条件（通过启动信号启动升压电路之后经过了预定时间段或者输出电压已经达到预定水平） 。 时钟的这种限制有助于抑制起动期间升压电路的功耗，从而减小电源电压的幅度变化。

公开(公告)号：US06324626B1

公开(公告)日：2001-11-27

申请号：US09108230

申请日：1998-07-01

申请人： Hiromi Uenoyama ,  Hiroki Takagi

发明人： Hiromi Uenoyama ,  Hiroki Takagi

IPC分类号： G06F1200

CPC分类号： G06F21/79 ,  G06F12/1433 ,  G11C7/1006 ,  G11C16/22

摘要： A semiconductor memory has a main memory and an ID memory, of which both store data in a nonvolatile memory. The data stored in the ID memory is compared with data entered from outside by a verifying circuit. Whether access to the main memory is permitted or not depends on the result of the verification by the verifying circuit. The operation code for accessing the ID memory is different from the operation code for accessing the main memory. The operation code for the ID memory is changed in accordance with the data stored in the ID memory.

摘要翻译： 半导体存储器具有将数据存储在非易失性存储器中的主存储器和ID存储器。 将存储在ID存储器中的数据与来自外部的验证电路进行比较。 允许访问主存储器是否取决于验证电路的验证结果。 用于访问ID存储器的操作代码与用于访问主存储器的操作代码不同。 ID存储器的操作代码根据存储在ID存储器中的数据而改变。

公开(公告)号：US5535162A

公开(公告)日：1996-07-09

申请号：US361871

申请日：1994-12-22

申请人： Hiromi Uenoyama

发明人： Hiromi Uenoyama

IPC分类号： G06F12/16 ,  G06F11/08 ,  G06F11/10 ,  G11C16/06 ,  G11C16/26 ,  G11C16/34 ,  G11C17/00 ,  G11C16/00

CPC分类号： G06F11/08 ,  G06F11/1076 ,  G11C16/26 ,  G11C16/349 ,  G11C16/3495

摘要： In an electrically erasable programmable ROM in which written data contains in a very limited part high-frequency reload data, the memory capacity is reduced in the following new way. An address detecting circuit (12) detects whether or not designated write addresses are within a predetermined range and discriminates the write object data, which is to be high-frequency reload data, if the designated write addresses are within the predetermined range as the result of detection. Then, three sets of identical data (D.sub.7 to D.sub.0) prepared by a data creating circuit (11) are overwritten respectively in three different memory cells (A.sub.0, A.sub.0 ', A.sub.0 "). In data reading, the individual data are read from the respective memory cells, and one of the data decided by a majority logical circuit (15) is outputted as read data.

摘要翻译： 在电可擦除可编程ROM中，其中写入数据在非常有限的部分中包含高频重载数据，以下列新方式减少存储器容量。 如果指定的写入地址在预定范围内，则地址检测电路（12）检测指定的写入地址是否在预定范围内，并且识别作为高频重载数据的写入对象数据，作为结果 检测。 然后，分别在三个不同的存储单元（A0，A0'，A0“）中重写由数据产生电路（11）准备的三组相同数据（D7至D0）。 在数据读取中，从相应的存储单元读取各个数据，并且由多数逻辑电路（15）决定的数据之一作为读取数据被输出。

公开(公告)号：US5305276A

公开(公告)日：1994-04-19

申请号：US943559

申请日：1992-09-11

申请人： Hiromi Uenoyama

发明人： Hiromi Uenoyama

IPC分类号： G11C17/00 ,  G11C11/00 ,  G11C16/02 ,  G11C16/10 ,  G11C8/00 ,  G11C7/00

CPC分类号： G11C16/105 ,  G11C11/005 ,  G11C16/102

摘要： A non-volatile IC memory comprising in addition to a PROM region divided into blocks a RAM region having a capacity corresponding to one of the blocks wherein the entire data stored in the corresponding block in the PROM region designated by an address sent out from the outside is transferred to the RAM region. After data in the corresponding portion in the RAM region designated by the address is rewritten by data sent out from the outside, the data in the RAM region is written back in the corresponding block of the PROM, thereby data is rewritten by a word unit or a bit unit.

摘要翻译： 一种非易失性IC存储器，包括除了PROM区域之外，其被划分为具有对应于其中一个块的容量的RAM区域的RAM区域，其中存储在由从外部发送的地址指定的地址指定的PROM区域中的相应块中的整个数据 被传输到RAM区域。 在由地址指定的RAM区域的对应部分中的数据被从外部发送的数据改写后，RAM区域中的数据被写回到PROM的相应块中，从而数据被字单元或 一个单位。

公开(公告)号：US5297101A

公开(公告)日：1994-03-22

申请号：US960807

申请日：1992-10-14

申请人： Yoshihiro Tada ,  Hiromi Uenoyama

发明人： Yoshihiro Tada ,  Hiromi Uenoyama

IPC分类号： G11C16/26 ,  G11C29/50 ,  G11C13/00

CPC分类号： G11C16/26 ,  G11C29/50 ,  G11C17/14 ,  G11C2029/5004

摘要： A PROM IC including sense circuits, each including a sense amplifier. A pull-up resistor circuit whose resistance value is variable is provided on the side of an input of the sense amplifier so that, upon a reception of a test selection signal, the resistance value of the resistor circuit is changed to a value with which a drive condition of current flowing through a selected memory cell becomes severe.

摘要翻译： 包括感测电路的PROM IC，每个包括读出放大器。 电阻值可变的上拉电阻电路设置在读出放大器的输入侧，使得在接收到测试选择信号时，将电阻电路的电阻值改变为 流过所选存储单元的电流的驱动条件变得严重。