公开(公告)号：US07233889B2

公开(公告)日：2007-06-19

申请号：US10278507

申请日：2002-10-23

申请人： Eiji Takahashi ,  Yoshiyuki Saito ,  Yukihiro Fukumoto ,  Hiroshi Benno

发明人： Eiji Takahashi ,  Yoshiyuki Saito ,  Yukihiro Fukumoto ,  Hiroshi Benno

IPC分类号： G06F17/50

CPC分类号： G06F17/5036

摘要： A method of evaluating noise immunity of a semiconductor device is provided. An actual circuit including the semiconductor device is represented by an equivalent circuit which has a target equivalent circuit, a noise source equivalent circuit, and an external equivalent circuit connected in parallel. The target equivalent circuit represents the semiconductor device. The noise source equivalent circuit represents a noise source outside the semiconductor device, and supplies noise to the target equivalent circuit. The external equivalent circuit represents a circuit outside the semiconductor device. The noise immunity is evaluated based on a voltage or current which arises in the target equivalent circuit by the noise. In this way, the immunity of the semiconductor device against extraneous noise can be evaluated in consideration of the effects of the circuitry outside the semiconductor device.

摘要翻译： 提供了一种评估半导体器件的抗噪声性的方法。 包括半导体器件的实际电路由具有并联连接的目标等效电路，噪声源等效电路和外部等效电路的等效电路表示。 目标等效电路表示半导体器件。 噪声源等效电路表示半导体器件外部的噪声源，并且将噪声提供给目标等效电路。 外部等效电路表示半导体器件外部的电路。 基于由噪声在目标等效电路中产生的电压或电流来评估噪声抗扰度。 以这种方式，可以考虑半导体器件外的电路的影响来评估半导体器件对外来噪声的抗扰性。

公开(公告)号：US06901343B2

公开(公告)日：2005-05-31

申请号：US10029571

申请日：2001-12-20

申请人： Eiji Takahashi ,  Yukihiro Fukumoto ,  Yoshiyuki Saito ,  Osamu Shibata ,  Shinichi Tanimoto ,  Takeshi Nakayama

发明人： Eiji Takahashi ,  Yukihiro Fukumoto ,  Yoshiyuki Saito ,  Osamu Shibata ,  Shinichi Tanimoto ,  Takeshi Nakayama

IPC分类号： G06F17/50 ,  H05K1/00 ,  H05K1/02 ,  H05K1/11 ,  H04L9/32

CPC分类号： G06F17/5068 ,  H05K1/0275 ,  H05K1/0298 ,  H05K1/114 ,  H05K2201/09627 ,  H05K2201/09772 ,  H05K2201/10151

摘要： A signal line, being in a six-layer board and connecting terminal 102 of component 101 with terminal 115 of component 114, requires tamper-resistance. The signal line is composed of foil 103 on an outside layer, a via 104, foil 111 on the third layer, via 105, foil 112 on the fourth layer, via 106, and foil 113 on the sixth layer. Portions of the signal line that exist on outside layers are all hidden under circuit components. Foil 103 and an end of via 104 are placed under component 101 on first layer 116, an end of via 105 is placed under component 107 on layer 116, an end of via 106 is placed under component 108 on layer 116, the other end of via 104 is placed under component 109 on sixth layer 121, the other end of via 105 is placed under component 110 on layer 121, and foil 113 and the other end of via 106 are placed under component 114 on layer 121.

摘要翻译： 在组件101的六层板和连接端子102与元件114的端子115之间的信号线需要防篡改。 信号线由外层的箔103，通孔104，第三层上的箔111，通孔105，第四层上的箔112，第106层和第六层上的箔113组成。 存在于外层的信号线部分都隐藏在电路元件下面。 箔103和通孔104的末端放置在第一层116上的部件101下方，通孔105的端部放置在层116上的部件107的下方，通孔106的端部放置在层116上的部件108的下方，另一端 通孔104被放置在第六层121上的部件109的下方，通孔105的另一端被放置在层121上的部件110下方，并且箔113和通孔106的另一端放置在层121上的部件114下方。