公开(公告)号：US11729898B1

公开(公告)日：2023-08-15

申请号：US17831859

申请日：2022-06-03

Applicant: TE Connectivity Solutions GmbH

Inventor： Justin Dennis Pickel ,  Margaret Mahoney Fernandes ,  Timothy Robert Minnick

IPC: H05K1/11 ,  H05K1/02 ,  H01R12/58 ,  H05K1/18

CPC classification number: H05K1/0222 ,  H05K1/116 ,  H01R12/58 ,  H05K1/18 ,  H05K2201/09481 ,  H05K2201/09609 ,  H05K2201/09772 ,  H05K2201/10189 ,  H05K2201/10901

Abstract: A printed circuit board includes a layered substrate having a plurality of layers having an electrical connector footprint configured to receive an electrical connector. The printed circuit board includes pair anti-pads passing through the layered substrate around pairs of signal vias. The printed circuit board includes ground vias passing through the layered substrate. The ground vias are configured to receive ground pins of the electrical connector. The ground vias are located outside of the pair anti-pads. The printed circuit board includes SI vias passing through the layered substrate. The SI vias form an SI fence surrounding the corresponding pair anti-pad.

公开(公告)号：US09282634B2

公开(公告)日：2016-03-08

申请号：US13953496

申请日：2013-07-29

Applicant: CANON KABUSHIKI KAISHA

Inventor： Masaharu Ohira

IPC: H05K7/02 ,  H05K1/11 ,  B23K31/02 ,  H05K1/02 ,  H05K13/04

CPC classification number: H05K1/0271 ,  H05K1/0207 ,  H05K1/113 ,  H05K13/0465 ,  H05K2201/09772

Abstract: Provided is a printed wiring board including a first heat dissipation pattern placed in one surface layer on which a semiconductor package is to be mounted, a second heat dissipation pattern placed in the other surface layer, and an inner layer conductor pattern placed in an inner layer, in which through holes are formed in the printed wiring board; the first heat dissipation pattern has a joint portion which is placed in an opposed region opposed to a heat sink of the semiconductor package and which is joined to the heat sink with solder; at least one of the through holes is placed in the opposed region; and the second heat dissipation pattern is formed in a pattern in which an end portion of a conductor film in the one of the through holes on the other surface layer side is separated.

Abstract translation: 提供一种印刷线路板，其包括放置在要安装半导体封装的一个表面层中的第一散热图案，设置在另一个表面层中的第二散热图案，以及放置在内层中的内层导体图案 ，其中在印刷线路板中形成有通孔; 第一散热图案具有接合部，该接合部设置在与半导体封装的散热器相对的相对区域中，并且利用焊料与散热器接合; 至少一个通孔被放置在相对的区域中; 并且第二散热图案形成为其中在另一表面层侧的一个通孔中的导体膜的端部分离的图案。

公开(公告)号：US08780575B2

公开(公告)日：2014-07-15

申请号：US13082258

申请日：2011-04-07

Applicant: Chih-Yung Chia

Inventor： Chih-Yung Chia

IPC: H05K1/18 ,  H05K1/02 ,  H05K1/11 ,  H05K3/00 ,  H05K3/28

CPC classification number: H05K1/02 ,  H05K1/111 ,  H05K3/0061 ,  H05K3/28 ,  H05K2201/0367 ,  H05K2201/09772 ,  H05K2201/09781 ,  H05K2201/2036

Abstract: A printed circuit board includes a board body having a routing-limited area. The routing-limited area is provided with at least one solder pad that is adapted for supporting a metal support thereon. Preferably, the printed circuit board further includes a protrusion block disposed on the solder pad, and having a height greater than that of a signal trace that passes the routing-limited area.

Abstract translation: 印刷电路板包括具有路由限制区域的板体。 布线限制区域设置有至少一个适于在其上支撑金属支撑件的焊盘。 优选地，印刷电路板还包括设置在焊盘上的突起块，其高度大于通过布线限制区域的信号迹线的高度。

公开(公告)号：US08368233B2

公开(公告)日：2013-02-05

申请号：US13159668

申请日：2011-06-14

Applicant: Yoshiharu Ogata

Inventor： Yoshiharu Ogata

IPC: H01L23/52

CPC classification number: H05K3/305 ,  H01L21/563 ,  H01L23/3128 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/83 ,  H01L25/0657 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/29007 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/83192 ,  H01L2225/06517 ,  H01L2225/06572 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H05K1/0271 ,  H05K3/3452 ,  H05K2201/09772 ,  H05K2201/10674 ,  H05K2201/10977 ,  Y02P70/613 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00011 ,  H01L2924/00014

Abstract: A semiconductor device comprises a wiring substrate including a wiring pattern; a semiconductor chip installed on the wiring substrate, including a plurality of pads formed on a surface of the semiconductor chip, which opposes the wiring substrate; a first resin layer covering over a part of the wiring pattern within a region of overlapping the semiconductor chip; and a second resin layer installed between the semiconductor chip and the first resin layer. The pads are oppose to and coupled with a part of the wiring pattern exposed over the first resin layer; and the linear expansion coefficient of the wiring substrate is larger than that of the semiconductor chip, the elastic modulus of the wiring substrate is lower than that of the semiconductor chip and the linear expansion coefficient of the first resin layer is larger than that of the second resin layer. The elastic modulus of the first resin layer is lower than that of the second resin layer.

Abstract translation: 半导体器件包括：布线基板，其包括布线图案; 安装在所述布线基板上的半导体芯片，包括与所述布线基板相对的形成在所述半导体芯片的表面上的多个焊盘; 覆盖所述布线图案的与所述半导体芯片重叠的区域的一部分上的第一树脂层; 以及安装在半导体芯片和第一树脂层之间的第二树脂层。 焊盘与暴露在第一树脂层上的布线图案的一部分相对并耦合; 并且布线基板的线膨胀系数大于半导体芯片的线膨胀系数，布线基板的弹性模量低于半导体芯片的弹性模量，并且第一树脂层的线膨胀系数大于第二树脂层的线膨胀系数 树脂层。 第一树脂层的弹性模量低于第二树脂层的弹性模量。

公开(公告)号：US08258409B2

公开(公告)日：2012-09-04

申请号：US12058040

申请日：2008-03-28

Applicant: Yasuhiro Kohara ,  Kiyoshi Shibata ,  Masayuki Nagamatsu ,  Ryosuke Usui ,  Toshiya Shimizu

Inventor： Yasuhiro Kohara ,  Kiyoshi Shibata ,  Masayuki Nagamatsu ,  Ryosuke Usui ,  Toshiya Shimizu

IPC: H05K1/00

CPC classification number: H05K3/383 ,  H01L23/3128 ,  H01L23/498 ,  H01L23/49838 ,  H01L23/564 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/056 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/48465 ,  H01L2224/48599 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/351 ,  H05K3/243 ,  H05K3/3452 ,  H05K2201/09727 ,  H05K2201/09772 ,  H05K2201/0989 ,  H05K2203/0307 ,  H05K2203/0361 ,  H05K2203/049 ,  H05K2203/0542 ,  H05K2203/0723 ,  H05K2203/1152 ,  H05K2203/1476 ,  Y10T29/49155 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05599

Abstract: Provided are a circuit board with enhanced moisture resist and the method of manufacturing the circuit board, and a circuit device and a method of manufacturing the circuit device. A circuit board of the present invention includes: a substrate; wirings formed on the main surface of the substrate; a cover layer covering the wirings excluding the regions to be connectors; back electrodes formed on the bottom surface of the substrate; and through-hole electrodes formed so as to penetrate the substrate, and thereby connecting the wirings and the back electrodes. On surfaces of each of the wirings in this circuit board, convex portions on the periphery of the substrate are set larger in width than convex portions in a center portion of the substrate. With this configuration, adhesion reliability between the wirings and the cover layer under a thermal cycle load can be enhanced.

Abstract translation: 提供了一种具有增强的抗湿性的电路板和制造该电路板的方法，以及电路装置和该电路装置的制造方法。 本发明的电路板包括：基板; 在基板的主表面上形成的布线; 覆盖除了作为连接器的区域的布线的覆盖层; 形成在基板的底面上的背面电极; 以及形成为穿透基板的通孔电极，从而连接布线和背面电极。 在该电路基板的各配线的表面上，基板周边的凸部的宽度比基板的中央部的凸部的宽度大。 利用这种结构，可以提高热循环负载下的布线与覆盖层之间的粘附可靠性。

公开(公告)号：US08236617B2

公开(公告)日：2012-08-07

申请号：US12794612

申请日：2010-06-04

Applicant: Reza A. Pagaila ,  Yaojian Lin ,  Jun Mo Koo

Inventor： Reza A. Pagaila ,  Yaojian Lin ,  Jun Mo Koo

IPC: H01L23/488 ,  H01L23/552 ,  H01L23/36 ,  H01L21/60

CPC classification number: H01L23/5389 ,  H01L21/561 ,  H01L21/568 ,  H01L23/295 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/36 ,  H01L23/367 ,  H01L23/3675 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/544 ,  H01L23/552 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/29 ,  H01L24/48 ,  H01L24/97 ,  H01L2221/68381 ,  H01L2221/68386 ,  H01L2223/54426 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/11849 ,  H01L2224/11901 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16225 ,  H01L2224/21 ,  H01L2224/2105 ,  H01L2224/215 ,  H01L2224/22 ,  H01L2224/221 ,  H01L2224/24195 ,  H01L2224/29 ,  H01L2224/29101 ,  H01L2224/29111 ,  H01L2224/29139 ,  H01L2224/29144 ,  H01L2224/29187 ,  H01L2224/2919 ,  H01L2224/29298 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48105 ,  H01L2224/48175 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/94 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15311 ,  H01L2924/1579 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/19105 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/351 ,  H01L2924/3511 ,  H05K1/0203 ,  H05K1/186 ,  H05K2201/09772 ,  H01L2924/01014 ,  H01L2924/05432 ,  H01L2924/0542 ,  H01L2924/0503 ,  H01L2924/00 ,  H01L2224/29099 ,  H01L2224/29199 ,  H01L2224/29299 ,  H01L2224/2929 ,  H01L2924/00012 ,  H01L2224/03 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device has a thermally conductive layer with a plurality of openings formed over a temporary carrier. The thermally conductive layer includes electrically non-conductive material. A semiconductor die has a plurality of bumps formed over contact pads on the die. The semiconductor die is mounted over the thermally conductive layer so that the bumps are disposed at least partially within the openings in the thermally conductive layer. An encapsulant is deposited over the die and thermally conductive layer. The temporary carrier is removed to expose the bumps. A first interconnect structure is formed over the encapsulant, semiconductor die, and bumps. The bumps are electrically connected to the first interconnect structure. A heat sink or shielding layer can be formed over the semiconductor die. A second interconnect structure can be formed over the encapsulant and electrically connected to the first interconnect structure through conductive vias formed in the encapsulant.

Abstract translation: 半导体器件具有形成在临时载体上的多个开口的导热层。 导热层包括非导电材料。 半导体管芯具有形成在管芯上的接触焊盘上的多个凸块。 半导体管芯安装在导热层上，使得凸块至少部分地设置在导热层的开口内。 密封剂沉积在管芯和导热层上。 移除临时载体以暴露凸块。 在密封剂，半导体管芯和凸块之上形成第一互连结构。 凸块电连接到第一互连结构。 可以在半导体管芯上形成散热器或屏蔽层。 第二互连结构可以形成在密封剂之上并且通过形成在密封剂中的导电通孔电连接到第一互连结构。

公开(公告)号：US20100182529A1

公开(公告)日：2010-07-22

申请号：US12647956

申请日：2009-12-28

Applicant: Daisuke NAKANISHI

Inventor： Daisuke NAKANISHI

IPC: G02F1/1333 ,  H05K7/00 ,  F21V8/00

CPC classification number: H04M1/22 ,  G02F1/1336 ,  G02F1/13452 ,  H05K1/0274 ,  H05K1/189 ,  H05K2201/09772 ,  H05K2201/09781 ,  H05K2201/10106 ,  H05K2201/2054

Abstract: A mount structure includes a wiring board and a semiconductor device composed of a light-emitting device or a light-receiving device mounted on one surface side of the wiring board such that an optical axis thereof is oriented in a direction that extends along a board surface of the wiring board. On the one surface side of the wiring board, a first pad on which a first terminal of the semiconductor device is mounted, a second pad on which a second terminal of the semiconductor device is mounted, and a light-shielding conductive layer are formed using the same conductive layer. The first pad and the second pad are arranged on respective sides of an imaginary center line along which the optical axis of the semiconductor device extends and the light-shielding conductive layer is provided at a position beneath a light emission center or a light reception center of the semiconductor device in plan view.

Abstract translation: 安装结构包括布线板和由安装在布线板的一个表面侧上的发光器件或光接收装置构成的半导体器件，使得其光轴沿着板表面延伸的方向定向 的接线板。 在布线板的一个表面侧上，安装半导体器件的第一端子的第一焊盘，安装半导体器件的第二端子的第二焊盘和遮光导电层，使用 相同的导电层。 第一焊盘和第二焊盘被布置在半导体器件的光轴延伸的假想中心线的两侧，并且遮光导电层设置在发光中心或光接收中心的下方的位置 该半导体器件在平面图中。

公开(公告)号：US07759799B2

公开(公告)日：2010-07-20

申请号：US11650459

申请日：2007-01-08

Applicant: Daisuke Ejima

Inventor： Daisuke Ejima

IPC: H01L23/48

CPC classification number: H01L23/3128 ,  H01L21/563 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/10 ,  H01L24/13 ,  H01L25/105 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/3511 ,  H05K1/111 ,  H05K3/3436 ,  H05K2201/09381 ,  H05K2201/094 ,  H05K2201/09772 ,  H05K2201/10734 ,  Y02P70/611 ,  H01L2924/00012 ,  H01L2924/00

Abstract: Aiming at adjusting the height of bump electrodes connected to lands on a substrate, a semiconductor device 100 has a first interconnect substrate 103 and a second interconnect substrate 101. On one surface of these substrates, first lands 111 and second lands 113 are provided. The plane geometry of the second lands 113 is a polygon characterized by the inscribed circle thereof having an area smaller than the area of the inscribed circle of the first land.

Abstract translation: 为了调整与衬底上的焊盘连接的突起电极的高度，半导体器件100具有第一互连衬底103和第二互连衬底101.在这些衬底的一个表面上设置有第一焊盘111和第二焊盘113。 第二平台113的平面几何形状是其内接圆的面积小于第一平台的内切圆的面积的多边形。

公开(公告)号：US20100090327A1

公开(公告)日：2010-04-15

申请号：US12637345

申请日：2009-12-14

Applicant: Yoshiharu OGATA

Inventor： Yoshiharu OGATA

IPC: H01L25/065 ,  H01L23/52 ,  H01L23/28

CPC classification number: H05K3/305 ,  H01L21/563 ,  H01L23/3128 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/83 ,  H01L25/0657 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/29007 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/83192 ,  H01L2225/06517 ,  H01L2225/06572 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H05K1/0271 ,  H05K3/3452 ,  H05K2201/09772 ,  H05K2201/10674 ,  H05K2201/10977 ,  Y02P70/613 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00011 ,  H01L2924/00014

Abstract: A semiconductor device comprises a wiring substrate including a wiring pattern; a semiconductor chip installed on the wiring substrate, including a plurality of pads formed on a surface of the semiconductor chip, which opposes the wiring substrate; a first resin layer covering over a part of the wiring pattern within a region of overlapping the semiconductor chip; and a second resin layer installed between the semiconductor chip and the first resin layer. The pads are oppose to and coupled with a part of the wiring pattern exposed over the first resin layer; and the linear expansion coefficient of the wiring substrate is larger than that of the semiconductor chip, the elastic modulus of the wiring substrate is lower than that of the semiconductor chip and the linear expansion coefficient of the first resin layer is larger than that of the second resin layer. The elastic modulus of the first resin layer is lower than that of the second resin layer.

Abstract translation: 半导体器件包括：布线基板，其包括布线图案; 安装在所述布线基板上的半导体芯片，包括与所述布线基板相对的形成在所述半导体芯片的表面上的多个焊盘; 覆盖所述布线图案的与所述半导体芯片重叠的区域的一部分上的第一树脂层; 以及安装在半导体芯片和第一树脂层之间的第二树脂层。 焊盘与暴露在第一树脂层上的布线图案的一部分相对并耦合; 并且布线基板的线膨胀系数大于半导体芯片的线膨胀系数，布线基板的弹性模量低于半导体芯片的弹性模量，并且第一树脂层的线膨胀系数大于第二树脂层的线膨胀系数 树脂层。 第一树脂层的弹性模量低于第二树脂层的弹性模量。

公开(公告)号：US07675729B2

公开(公告)日：2010-03-09

申请号：US10582758

申请日：2004-12-22

Applicant: David Anthony ,  Anthony Anthony ,  William M. Anthony ,  James Muccioli ,  Richard A. Neifeld

Inventor： David Anthony ,  Anthony Anthony ,  William M. Anthony ,  James Muccioli ,  Richard A. Neifeld

IPC: H02H9/00

CPC classification number: H01G4/35 ,  H01L23/552 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01P1/203 ,  H05K1/0233 ,  H05K2201/09254 ,  H05K2201/0969 ,  H05K2201/09772 ,  H05K2201/09781 ,  H05K2201/1006 ,  H05K2201/10454 ,  H05K2201/10636 ,  Y02P70/611 ,  H01L2924/00

Abstract: An energy conditioner structure comprising a first electrode (120), a second electrode (80), and a shield structure (70, 110, 150) provides improved energy conditioning in electrical circuits. The structures may exist as discrete components or part of an integrated circuit. The shield structure in the energy conditioner structure does not electrically connect to any circuit element.

Abstract translation: 包括第一电极（120），第二电极（80）和屏蔽结构（70,110,150）的能量调节器结构在电路中提供改进的能量调节。 结构可以作为分立组件或集成电路的一部分存在。 能量调节器结构中的屏蔽结构不电连接到任何电路元件。