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11.发明授权Square root extraction circuit and floating-point square root extraction device 失效平方根提取电路和浮点平方根提取装置
公开(公告)号：US6148318A
公开(公告)日：2000-11-14
申请号：US964888
申请日：1997-11-05
CPC分类号： G06F7/5525 , G06F7/483
摘要： A square root extraction circuit and a floating-point square root extraction device which simplify a circuit structure and improve an operation speed are provided. Portions for generating square root partial data (q3 to q8) include carry output prediction circuits (3 to 8), respectively. The carry output prediction circuit (i) (i equals any one of 3 to 8) receives condition flags (AHin, ALin), the most significant addition result (SUM), and square root partial data (q(i-1)) from the preceding square root partial data generating portion, and also receives a carry input (Cin) to output condition flags (AHout, ALout) for the next square root partial data generating portion, and square root partial data (q(i)). The condition flags (AHout, ALout) serve as the condition flags (AHin, ALin) for the carry output prediction circuit (i+1), respectively.
摘要翻译： 提供了简化电路结构并提高操作速度的平方根提取电路和浮点平方根提取装置。 用于产生平方根部分数据（q3至q8）的部分分别包括进位输出预测电路（3至8）。 进位输出预测电路（i）（i等于3至8中的任何一个）从第一个输入预测电路（i）中接收条件标志（AHin，ALin），最高有效相加结果（SUM）和平方根部分数据（q（i-1） 前一平方根部分数据生成部分，并且还接收用于下一个平方根部分数据生成部分的输出条件标志（AHout，ALout）的进位输入（Cin）和平方根部分数据（q（i））。 条件标志（AHout，ALout）分别用作进位输出预测电路（i + 1）的条件标志（AHin，ALin）。
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12.发明授权SIMD processor operating with a plurality of parallel processing elements in synchronization 失效SIMD处理器同时处理多个并行处理元件
公开(公告)号：US5729758A
公开(公告)日：1998-03-17
申请号：US465245
申请日：1995-06-05
IPC分类号： G06F9/38 , G06F15/16 , G06F15/173 , G06F15/80
CPC分类号： G06F15/8015 , G06F9/3893
摘要： Three local buses and three composite operation buses are provided in each processing element. An arithmetic logic unit, a multiplier, a bit operator, and an accumulator are connected to respective local buses and the composite operation buses. As a result, each operation unit can transfer data efficiently using a plurality of buses of different functions.
摘要翻译： 在每个处理元件中提供三条本地总线和三条复合操作总线。 算术逻辑单元，乘法器，位操作器和累加器连接到相应的本地总线和复合操作总线。 结果，每个操作单元可以使用具有不同功能的多个总线来有效地传送数据。
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13.发明授权Square root extraction circuit and floating-point square root extraction device 失效平方根提取电路和浮点平方根提取装置公开(公告)号：US06820107B1
公开(公告)日：2004-11-16
申请号：US09667783
申请日：2000-09-22
IPC分类号： G06F738
CPC分类号： G06F7/5525 , G06F7/483
摘要： A square root extraction circuit and a floating-point square root extraction device which simplify a circuit structure and improve an operation speed are provided. Portions for generating square root partial data (q3 to q8) include carry output prediction circuits (3 to 8), respectively. The carry output prediction circuit (i) (i equals any one of 3 to 8) receives condition flags (AHin, ALin), the most significant addition result (SUM), and square root partial data (q(i−1)) from the preceding square root partial data generating portion, and also receives a carry input (Cin) to output condition flags (AHout, ALout) for the next square root partial data generating portion, and square root partial data (q(i)). The condition flags (AHout, ALout) serve as the condition flags (AHin, ALin) for the carry output prediction circuit (i+1), respectively.
摘要翻译： 提供了简化电路结构并提高操作速度的平方根提取电路和浮点平方根提取装置。 用于产生平方根部分数据（q3至q8）的部分分别包括进位输出预测电路（3至8）。 进位输出预测电路（i）（i等于3至8中的任何一个）从第一个输入预测电路（i）中接收条件标志（AHin，ALin），最高有效相加结果（SUM）和平方根部分数据（q（i-1） 前一平方根部分数据生成部分，并且还接收用于下一个平方根部分数据生成部分的输出条件标志（AHout，ALout）的进位输入（Cin）和平方根部分数据（q（i））。 条件标志（AHout，ALout）分别用作进位输出预测电路（i + 1）的条件标志（AHin，ALin）。
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14.发明授权Image processing LSI circuit with image preprocessing, feature extraction and matching 失效图像处理LSI电路，具有图像预处理，特征提取和匹配
公开(公告)号：US5715436A
公开(公告)日：1998-02-03
申请号：US510125
申请日：1995-08-01
CPC分类号： G06T1/20
摘要： There is disclosed a high-speed programmable image processing LSI circuit adaptable to image preprocessing, feature extraction, and matching, which includes a DMA transfer control portion (4) for DMA transfer which reads input data from an external memory to transfer the input data to data memories in the LSI circuit; a sequence control portion (8), an instruction memory (7), and an address generating portion (3) which control writing to and reading from the data memories in response to an instruction code; the DMA transfer control portion (4) accommodating a wait time caused during external data transfer to prevent the wait time from affecting instruction code control in the LSI circuit; SIMD type processing units arranged in parallel and connected to output lines of the data memories for completing the process steps of image processing in cooperation with a postprocessing portion which in turn provides an output signal (54) to the exterior and accommodates a wait time at this time.
摘要翻译： 公开了一种适用于图像预处理，特征提取和匹配的高速可编程图像处理LSI电路，其包括用于DMA传输的DMA传输控制部分（4），其从外部存储器读取输入数据以将输入数据传送到 LSI电路中的数据存储器; 序列控制部分（8），指令存储器（7）和地址生成部分（3），其响应于指令代码控制对数据存储器的写入和读取; DMA传送控制部分（4）容纳在外部数据传输期间引起的等待时间，以防止等待时间影响LSI电路中的指令代码控制; SIMD型处理单元并联布置并连接到数据存储器的输出线，用于与后处理部分协作完成图像处理的处理步骤，后处理部分进一步向外部提供输出信号（54）并且在此处提供等待时间 时间。
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15.发明授权PCI-PCI bridge allowing controlling of a plurality of PCI agents including a VGA device 失效允许控制包括VGA设备的多个PCI代理的PCI-PCI桥公开(公告)号：US06272582B1
公开(公告)日：2001-08-07
申请号：US09140317
申请日：1998-08-26
IPC分类号： G06F1300
CPC分类号： G06F13/4027
摘要： A PCI-PCI bridge is connected between a primary PCI bus and a secondary PCI bus, and includes a bridge for connecting the secondary PCI bus to the primary PCI bus. The bridge has a type “00” configuration header, and identifies, at the time of configuration, one of a plurality of PCI agents including a VGA device on the secondary PCI bus based on a value of a function number field of the configuration command from the device driver, and that the identified agent to execute configuration.
摘要翻译： PCI-PCI桥接器连接在主PCI总线和辅助PCI总线之间，并且包括用于将辅助PCI总线连接到主PCI总线的桥。 该桥具有类型“00”配置头，并且在配置时，基于辅助PCI总线上的VGA设备，基于配置命令的功能号字段的值来识别配置时的多个PCI代理之一 设备驱动程序，以及所识别的代理执行配置。
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