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1.发明授权Square root extraction circuit and floating-point square root extraction device 失效平方根提取电路和浮点平方根提取装置
公开(公告)号：US6148318A
公开(公告)日：2000-11-14
申请号：US964888
申请日：1997-11-05
CPC分类号： G06F7/5525 , G06F7/483
摘要： A square root extraction circuit and a floating-point square root extraction device which simplify a circuit structure and improve an operation speed are provided. Portions for generating square root partial data (q3 to q8) include carry output prediction circuits (3 to 8), respectively. The carry output prediction circuit (i) (i equals any one of 3 to 8) receives condition flags (AHin, ALin), the most significant addition result (SUM), and square root partial data (q(i-1)) from the preceding square root partial data generating portion, and also receives a carry input (Cin) to output condition flags (AHout, ALout) for the next square root partial data generating portion, and square root partial data (q(i)). The condition flags (AHout, ALout) serve as the condition flags (AHin, ALin) for the carry output prediction circuit (i+1), respectively.
摘要翻译： 提供了简化电路结构并提高操作速度的平方根提取电路和浮点平方根提取装置。 用于产生平方根部分数据（q3至q8）的部分分别包括进位输出预测电路（3至8）。 进位输出预测电路（i）（i等于3至8中的任何一个）从第一个输入预测电路（i）中接收条件标志（AHin，ALin），最高有效相加结果（SUM）和平方根部分数据（q（i-1） 前一平方根部分数据生成部分，并且还接收用于下一个平方根部分数据生成部分的输出条件标志（AHout，ALout）的进位输入（Cin）和平方根部分数据（q（i））。 条件标志（AHout，ALout）分别用作进位输出预测电路（i + 1）的条件标志（AHin，ALin）。
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2.发明授权Square root extraction circuit and floating-point square root extraction device 失效平方根提取电路和浮点平方根提取装置公开(公告)号：US06820107B1
公开(公告)日：2004-11-16
申请号：US09667783
申请日：2000-09-22
IPC分类号： G06F738
CPC分类号： G06F7/5525 , G06F7/483
摘要： A square root extraction circuit and a floating-point square root extraction device which simplify a circuit structure and improve an operation speed are provided. Portions for generating square root partial data (q3 to q8) include carry output prediction circuits (3 to 8), respectively. The carry output prediction circuit (i) (i equals any one of 3 to 8) receives condition flags (AHin, ALin), the most significant addition result (SUM), and square root partial data (q(i−1)) from the preceding square root partial data generating portion, and also receives a carry input (Cin) to output condition flags (AHout, ALout) for the next square root partial data generating portion, and square root partial data (q(i)). The condition flags (AHout, ALout) serve as the condition flags (AHin, ALin) for the carry output prediction circuit (i+1), respectively.
摘要翻译： 提供了简化电路结构并提高操作速度的平方根提取电路和浮点平方根提取装置。 用于产生平方根部分数据（q3至q8）的部分分别包括进位输出预测电路（3至8）。 进位输出预测电路（i）（i等于3至8中的任何一个）从第一个输入预测电路（i）中接收条件标志（AHin，ALin），最高有效相加结果（SUM）和平方根部分数据（q（i-1） 前一平方根部分数据生成部分，并且还接收用于下一个平方根部分数据生成部分的输出条件标志（AHout，ALout）的进位输入（Cin）和平方根部分数据（q（i））。 条件标志（AHout，ALout）分别用作进位输出预测电路（i + 1）的条件标志（AHin，ALin）。
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3.发明授权Geometry processor capable of executing input/output and high speed geometry calculation processing in parallel 有权能够并行执行输入/输出和高速几何计算处理的几何处理器公开(公告)号：US06603481B1
公开(公告)日：2003-08-05
申请号：US09294002
申请日：1999-04-19
申请人： Hiroyuki Kawai , Robert Streitenberger , Yoshitsugu Inoue , Keijiro Yoshimatsu , Junko Kobara , Hiroyasu Negishi
发明人： Hiroyuki Kawai , Robert Streitenberger , Yoshitsugu Inoue , Keijiro Yoshimatsu , Junko Kobara , Hiroyasu Negishi
IPC分类号： G06F1580
CPC分类号： G06F15/8007
摘要： The geometry processor includes mutually independent first and second external interface ports connected to a host processor, and a rendering processor, respectively, and a geometry calculation core which processes a geometry calculation applied through the first external interface port from the host processor. The geometry calculation core includes a plurality of SIMD type floating point calculating units, a floating point power computing unit, an integer calculating unit, a controller responsive to an instruction from the host processor which controls the plurality of floating point calculating units, the floating point power computing unit and the integer calculating unit to process data from the host processor, and an output controller which outputs the processed data to the rendering processor through the second external interface port.
摘要翻译： 几何处理器包括分别连接到主机处理器和渲染处理器的相互独立的第一和第二外部接口端口以及处理通过第一外部接口端口从主机处理器应用的几何计算的几何计算核心。 几何计算核心包括多个SIMD型浮点计算单元，浮点计算单元，整数计算单元，响应于来自主处理器的控制多个浮点计算单元的指令的控制器，浮点 功率计算单元和用于处理来自主处理器的数据的整数计算单元，以及输出控制器，其通过第二外部接口端口将处理后的数据输出到渲染处理器。
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4.发明授权
公开(公告)号：US5657485A
公开(公告)日：1997-08-12
申请号：US509940
申请日：1995-08-01
IPC分类号： G06F9/32
CPC分类号： G06F9/325 , G06F9/30065
摘要： The present invention is directed to a program control unit which enables a program control to achieve an efficient loop processing which does not immediately follow a loop instruction and which contains a start address and end address. In the program control unit, the start address and end address of a loop processing are stored in a register (start) (7) and a register (end) (8), respectively, in synchronization with a clock t1. The stored data "start" of the register (7) and the stored data "end" of the register (8) are inputted to a comparator (12) and a comparator (11), respectively. The comparator (12) compares the output from a delay program counter (18) with the data "start", and sets a flag f start when the comparison result indicates agreement and otherwise resets it. The comparator (11) compares the output from a delay program counter (18) with the data "end", and sets a flag f end when the comparison result indicates agreement and otherwise resets it.
摘要翻译： 本发明涉及一种程序控制单元，其使得程序控制能够实现不立即循环指令并且包含开始地址和结束地址的有效的循环处理。 在程序控制单元中，循环处理的起始地址和结束地址分别与时钟t1同步地存储在寄存器（起始）（7）和寄存器（结束）（8）中。 寄存器（7）的存储数据“开始”和寄存器（8）的存储数据“结束”分别输入到比较器（12）和比较器（11）。 比较器（12）将来自延迟程序计数器（18）的输出与数据“开始”进行比较，并且当比较结果指示一致时设置标志f开始，否则将其复位。 比较器（11）将来自延迟程序计数器（18）的输出与数据“结束”进行比较，并且当比较结果表示协议时设定标志f结束，否则将其复位。
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5.发明申请Assembler capable of reducing size of object code, and processor for executing the object code 审中-公开能够减少对象代码大小的汇编器和用于执行目标代码的处理器公开(公告)号：US20050108698A1
公开(公告)日：2005-05-19
申请号：US10841467
申请日：2004-05-10
IPC分类号： G06F9/45
CPC分类号： G06F8/4434
摘要： An instruction analyzing unit sequentially analyzes instructions of a program which is inputted to a program inputting unit. A NOP instruction analyzing part encodes continuous NOP instructions as one continuous NOP instruction. An instruction code outputting unit outputs the instruction encoded by the instruction analyzing unit as an object code. Therefore, the size of the object code can be reduced.
摘要翻译： 指令分析单元顺序地分析输入到程序输入单元的程序的指令。 NOP指令分析部分将连续的NOP指令编码为一个连续的NOP指令。 指令代码输出单元将由指令分析单元编码的指令作为目标代码输出。 因此，可以减少目标代码的大小。
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6.发明授权公开(公告)号：US06711601B2
公开(公告)日：2004-03-23
申请号：US09775513
申请日：2001-02-05
IPC分类号： G06F7556
CPC分类号： G06F1/0307 , G06F1/035
摘要： A logarithmic arithmetic unit includes first logarithmic operation part multiplying an exponent part of floating-point data by a prescribed value, a logarithmic table memory outputting a logarithmic value corresponding to bit data expressing a digit higher than a prescribed digit of a fixed-point part of the floating-point data, divisional precision decision part deciding divisional precision on the basis of the exponent part, division part performing division on a dividend obtained by subtracting the bit data from the fixed-point part and a divisor of the bit data and obtaining a result of division of a number of digits set on the basis of the divisional precision, second logarithmic operation part obtaining the logarithmic value of a value obtained by dividing the fixed-point part by the bit data and sum operation part adding outputs from the first and second logarithmic operation parts and the logarithmic table memory to each other.
摘要翻译： 对数算术单元包括将浮点数据的指数部分乘以规定值的第一对数运算部，对数表存储器输出对应于与比特数据对应的对数值，比特数据表示高于定点部分的规定数位 所述浮点数据，分割精度判定部根据所述指数部判定分割精度，对所述定点部分减去所述位数据和所述位数据的除数进行除法而得到的除数， 基于分割精度设定的数位分割结果，第二对数运算部分求出通过将定点部分除以比特数据而获得的值的对数值和加法运算部分的加法运算部分，从第一和第 第二对数运算部分和对数表存储器。
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公开(公告)号：US07054979B2
公开(公告)日：2006-05-30
申请号：US09985009
申请日：2001-11-01
IPC分类号： G06F13/14
CPC分类号： H04L12/4625
摘要： The method of routing configuration accesses applied from the primary port to a plurality of secondary ports includes the steps of: distributing a plurality of configuration accesses received from the primary bus to the plurality of secondary ports in accordance with a predetermined algorithm, such that each of the devices on the secondary ports receives and responds to exactly a single access; and terminating configuration cycles after distributing the plurality of configuration accesses.
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公开(公告)号：US06442627B1
公开(公告)日：2002-08-27
申请号：US09453547
申请日：1999-12-03
申请人： Hiroyasu Negishi , Junko Kobara , Yoshitsugu Inoue , Hiroyuki Kawai , Keijiro Yoshimatsu , Nelson Chan , Robert Streitenberger
发明人： Hiroyasu Negishi , Junko Kobara , Yoshitsugu Inoue , Hiroyuki Kawai , Keijiro Yoshimatsu , Nelson Chan , Robert Streitenberger
IPC分类号： G06F300
摘要： An output FIFO data transfer control device can comprise a geometric arithmetic core including one integer processing unit or IPU and a plurality of floating-point processing units or FPUs. Each processing unit includes an intermediate buffer or data output buffer for storing a data on an arithmetic result. When an instruction of data transfer from at least one of the plurality of processing units to one output FIFO is issued, a write/read pointer generating unit generates a write pointer identifying a specific location where data on an arithmetic result associated with the instruction is to be stored in the intermediate buffer of at least one of the plurality of processing units. The write/read pointer generating unit also generates a read pointer identifying a specific location where data is to be read out of the intermediate buffer of at least one of the plurality of processing units. A transfer mode setting unit sets a transfer mode identifying which at least one of the plurality of processing units is to transfer data on an arithmetic result, and sequentially furnishes a read enable signal to at least one of the plurality of processing units so as to read out the data from the intermediate buffer of at least one of the plurality of processing units.
摘要翻译： 输出FIFO数据传送控制装置可以包括包括一个整数处理单元或IPU以及多个浮点处理单元或FPU的几何运算核心。 每个处理单元包括用于存储关于算术结果的数据的中间缓冲器或数据输出缓冲器。 当发出从多个处理单元中的至少一个处理单元到一个输出FIFO的数据传送指令时，写入/读出指针生成单元产生一个写入指针，该指针识别与该指令相关联的算术结果的数据为 被存储在多个处理单元中的至少一个处理单元的中间缓冲器中。 写/读指针生成单元还生成识别要从多个处理单元中的至少一个的中间缓冲器读出数据的特定位置的读指针。 传送模式设置单元设置传送模式，其识别多个处理单元中的至少一个处理单元是在算术结果上传送数据，并且将读取使能信号顺序地提供给多个处理单元中的至少一个，以便读取 从多个处理单元中的至少一个的中间缓冲器输出数据。
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9.发明授权SIMD processor operating with a plurality of parallel processing elements in synchronization 失效SIMD处理器同时处理多个并行处理元件
公开(公告)号：US5729758A
公开(公告)日：1998-03-17
申请号：US465245
申请日：1995-06-05
IPC分类号： G06F9/38 , G06F15/16 , G06F15/173 , G06F15/80
CPC分类号： G06F15/8015 , G06F9/3893
摘要： Three local buses and three composite operation buses are provided in each processing element. An arithmetic logic unit, a multiplier, a bit operator, and an accumulator are connected to respective local buses and the composite operation buses. As a result, each operation unit can transfer data efficiently using a plurality of buses of different functions.
摘要翻译： 在每个处理元件中提供三条本地总线和三条复合操作总线。 算术逻辑单元，乘法器，位操作器和累加器连接到相应的本地总线和复合操作总线。 结果，每个操作单元可以使用具有不同功能的多个总线来有效地传送数据。
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10.发明授权Graphic processor having multiple geometric operation units and method of processing data thereby 有权具有多个几何运算单元的图形处理器和由此处理数据的方法公开(公告)号：US06795075B1
公开(公告)日：2004-09-21
申请号：US09685895
申请日：2000-10-11
IPC分类号： G06F1516
CPC分类号： G06T15/005
摘要： A graphic processor includes first and second buses and a plurality of geometric operation units having an output connected to the second bus, and a circuit to allocate a plurality of ordered data blocks formed of data to be operated upon to the plurality of geometric operation units, and an input of at least one of the plurality of geometric operation units is connected to the first bus. The plurality of geometric operation units include all arbitrating circuit to arbitrate the order of output between an output buffer to store a result of processing by the allocated data blocks and another geometric operation unit, and output data resulting from processing onto the second bus in an order corresponding to the sequence of the plurality of data blocks of data to be operated upon.
摘要翻译： 图形处理器包括第一和第二总线以及具有连接到第二总线的输出的多个几何运算单元，以及分配由多个几何运算单元运行的数据构成的多个有序数据块的电路， 并且所述多个几何运算单元中的至少一个的输入连接到所述第一总线。 多个几何运算单元包括用于仲裁输出缓冲器之间的输出顺序的所有仲裁电路，用于存储由分配的数据块和另一几何运算单元进行的处理结果，并且以按顺序将从处理得到的处理结果输出到第二总线上 对应于要被操作的数据的多个数据块的序列。
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