公开(公告)号：US10409766B2

公开(公告)日：2019-09-10

申请号：US15845450

申请日：2017-12-18

Applicant: Huawei Technologies Co., Ltd.

Inventor： Jiangen Liu ,  Chenghong He ,  Haibin Wang ,  Xinyu Hou

IPC: G06F9/30 ,  G06F15/80 ,  G06F15/173 ,  G06F15/167 ,  G06F13/42

Abstract: A computer subsystem and a computer system, where the computer subsystem includes L composite nodes (CNs), each CN includes M basic nodes, each basic node includes N central processing units (CPUs) and one node controller (NC). Any two CPUs in each basic node are interconnected. Each CPU in each basic node is connected to the NC in the basic node. The NC in each basic node has a routing function. Any two NCs in the M basic nodes are interconnected. A connection between the L CNs formed through connections between NCs enables communication between any two NCs to be no more than three hops. Hence, the computer subsystem and the computer system can reduce the kinds and the number of interconnection chips, and simplify an interconnection structure of a system, thereby improving reliability of the system.

公开(公告)号：US20190229997A1

公开(公告)日：2019-07-25

申请号：US16371909

申请日：2019-04-01

Applicant: Huawei Technologies Co., Ltd.

Inventor： Jie Cheng ,  Haibin Wang ,  Yanhua Li

IPC: H04L12/24

Abstract: A network distance prediction method and apparatus, wherein the method includes: communicating, with at least two reference nodes, to determine values of at least some elements in a local distance matrix; constructing, the local distance matrix based on the values of the at least some elements in the local distance matrix; performing, low-rank sparse factorization on the local distance matrix to obtain a low-rank matrix; obtaining, values of elements in a first element set of the low-rank matrix, to use the values as target values of network distances between the to-be-positioned node and the at least two reference nodes; communicating, with the reference nodes, to obtain coordinates of the reference nodes in a network coordinate system; and determining, coordinates of the to-be-positioned node. The embodiments of the present invention can improve accuracy of network distance prediction.

公开(公告)号：US08909979B2

公开(公告)日：2014-12-09

申请号：US13707188

申请日：2012-12-06

Applicant: Huawei Technologies Co., Ltd.

Inventor： Sheng Chang ,  Haibin Wang ,  Jie Zhang ,  Rongyu Yang ,  Xinyu Hou

IPC: G06F11/00 ,  G06F11/20 ,  G06F11/07 ,  G06F11/14

CPC classification number: G06F11/2005 ,  G06F11/0724 ,  G06F11/0745 ,  G06F11/0784 ,  G06F11/1443

Abstract: A system for implementing interconnection fault tolerance between CPUs, a first CPU and a second CPU implements interconnection through a first CPU interconnect device and a second CPU interconnect device. The system adds a data channel between a first SerDes interface of the first CPU interconnect device and a second SerDes interface of the second CPU interconnect device, and transmits link connection state information and a link control signal through the added data channel. The system monitors a link state of any one link in a CPU interconnection system, transmits the link state through the added data channel, recovers any one of the connection links when determining whether any one of the first connection link, the second connection link and the third connection link is faulty.

Abstract translation: 用于实现CPU之间的互连容错的系统，第一CPU和第二CPU通过第一CPU互连设备和第二CPU互连设备实现互连。 该系统在第一CPU互连设备的第一SerDes接口和第二CPU互连设备的第二SerDes接口之间添加数据信道，并通过添加的数据信道发送链路连接状态信息和链路控制信号。 系统监视CPU互连系统中任一链路的链路状态，通过添加的数据信道发送链路状态，在确定第一连接链路，第二连接链路和 第三连接链路故障。

公开(公告)号：US20130097455A1

公开(公告)日：2013-04-18

申请号：US13707188

申请日：2012-12-06

Applicant: Huawei Technologies Co., Ltd.

Inventor： Sheng Chang ,  Haibin Wang ,  Jie Zhang ,  Rongyu Yang ,  Xinyu Hou

IPC: G06F11/20

CPC classification number: G06F11/2005 ,  G06F11/0724 ,  G06F11/0745 ,  G06F11/0784 ,  G06F11/1443

Abstract: A system for implementing interconnection fault tolerance between CPUs, a first CPU and a second CPU implements interconnection through a first CPU interconnect device and a second CPU interconnect device. The system adds a data channel between a first SerDes interface of the first CPU interconnect device and a second SerDes interface of the second CPU interconnect device, and transmits link connection state information and a link control signal through the added data channel. The system monitors a link state of any one link in a CPU interconnection system, transmits the link state through the added data channel, recovers any one of the connection links when determining whether any one of the first connection link, the second connection link and the third connection link is faulty.

Abstract translation: 用于实现CPU之间的互连容错的系统，第一CPU和第二CPU通过第一CPU互连设备和第二CPU互连设备实现互连。 该系统在第一CPU互连设备的第一SerDes接口和第二CPU互连设备的第二SerDes接口之间添加数据信道，并通过添加的数据信道发送链路连接状态信息和链路控制信号。 系统监视CPU互连系统中任一链路的链路状态，通过添加的数据信道发送链路状态，在确定第一连接链路，第二连接链路和 第三连接链路故障。