公开(公告)号：US09148264B2

公开(公告)日：2015-09-29

申请号：US14502326

申请日：2014-09-30

Applicant: Huawei Technologies Co., Ltd.

Inventor： Xinyu Hou ,  Sheng Chang ,  Rongyu Yang ,  Guang Lu

IPC: H04L1/24 ,  H04L1/18 ,  H04L1/20 ,  G06F11/07 ,  G06F11/263 ,  H04L1/08

CPC classification number: H04L1/24 ,  G06F11/076 ,  G06F11/263 ,  H04L1/0045 ,  H04L1/0061 ,  H04L1/08 ,  H04L1/1635 ,  H04L1/18 ,  H04L1/1825 ,  H04L1/1874 ,  H04L1/20 ,  H04L1/203 ,  H04L1/244

Abstract: A data transmission method, device and system to improve reliability of a data link. When the sender side detects erroneous data, the erroneous data is discarded and a data retransmission request is sent to the sender side to ensure correctness of received data and improve reliability of the data link; and, when the sender side detects the erroneous data and a bit error rate is greater than a preset bit error rate threshold, the data link gets into auto recovery, and data transmission is resumed after the recovery succeeds, thereby avoiding an excessively high bit error rate, preventing an excessively high probability of omitted checks (the higher the bit error rate is, the higher probability of omitted checks is), and further improving reliability of the data link.

Abstract translation: 一种提高数据链路可靠性的数据传输方法，设备和系统。 当发送方检测到错误数据时，丢弃错误数据，并向发送方发送数据重发请求，以确保接收到的数据的正确性并提高数据链路的可靠性; 并且当发送方检测到错误数据并且误码率大于预设误码率阈值时，数据链路进入自动恢复，并且在恢复成功之后恢复数据传输，从而避免了过高的位错误 速率，防止忽略检查的概率过高（误码率越高，省略检查的概率越高），并进一步提高数据链路的可靠性。

公开(公告)号：US11818036B2

公开(公告)日：2023-11-14

申请号：US17990942

申请日：2022-11-21

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Rongyu Yang ,  Yumin Wu ,  Tianchi Hu ,  Tao Li

IPC: H04L45/24 ,  H04L49/253

CPC classification number: H04L45/245 ,  H04L49/253

Abstract: In a data processing method, a timeout aggregation node of a cluster obtains first data that is partial aggregated data in a data-intensive computing task. The first data carries a first identifier of a timeout node indicating that a timeout occurs on the timeout node. The timeout aggregation node obtains second data of the timeout node based on the first identifier, where the second data is to-be-aggregated data sent by the timeout node. The timeout aggregation node aggregates the first data and the second data according to a preset rule to obtain third data that is complete aggregated data. The timeout aggregation node then notifies each computing node in the cluster of the third data.

公开(公告)号：US20220191153A1

公开(公告)日：2022-06-16

申请号：US17683600

申请日：2022-03-01

Applicant: Huawei Technologies Co., Ltd.

Inventor： Lei Huang ,  Tao Li ,  Rongyu Yang

IPC: H04L49/00

Abstract: An intermediate device in a computer device includes a first agent unit supporting single-root input/output (I/O) virtualization (SR-IOV) and a second agent unit supporting Virtio, and the first agent unit and the second agent unit each are an agent of a function unit in a network adapter such that, a virtual machine in the computer device may use an SR-IOV technology or a Virtio technology, and does not configure two sets of independent resource pools to separately support corresponding virtualization technologies, to implement normalization of the resource pools. In addition, the intermediate device implements hardware offloading of Virtio protocol packet forwarding using hardware.

公开(公告)号：US20130097455A1

公开(公告)日：2013-04-18

申请号：US13707188

申请日：2012-12-06

Applicant: Huawei Technologies Co., Ltd.

Inventor： Sheng Chang ,  Haibin Wang ,  Jie Zhang ,  Rongyu Yang ,  Xinyu Hou

IPC: G06F11/20

CPC classification number: G06F11/2005 ,  G06F11/0724 ,  G06F11/0745 ,  G06F11/0784 ,  G06F11/1443

Abstract: A system for implementing interconnection fault tolerance between CPUs, a first CPU and a second CPU implements interconnection through a first CPU interconnect device and a second CPU interconnect device. The system adds a data channel between a first SerDes interface of the first CPU interconnect device and a second SerDes interface of the second CPU interconnect device, and transmits link connection state information and a link control signal through the added data channel. The system monitors a link state of any one link in a CPU interconnection system, transmits the link state through the added data channel, recovers any one of the connection links when determining whether any one of the first connection link, the second connection link and the third connection link is faulty.

Abstract translation: 用于实现CPU之间的互连容错的系统，第一CPU和第二CPU通过第一CPU互连设备和第二CPU互连设备实现互连。 该系统在第一CPU互连设备的第一SerDes接口和第二CPU互连设备的第二SerDes接口之间添加数据信道，并通过添加的数据信道发送链路连接状态信息和链路控制信号。 系统监视CPU互连系统中任一链路的链路状态，通过添加的数据信道发送链路状态，在确定第一连接链路，第二连接链路和 第三连接链路故障。

公开(公告)号：US12273283B2

公开(公告)日：2025-04-08

申请号：US17683600

申请日：2022-03-01

Applicant: Huawei Technologies Co., Ltd.

Inventor： Lei Huang ,  Tao Li ,  Rongyu Yang

IPC: H04L49/00

Abstract: An intermediate device in a computer device includes a first agent unit supporting single-root input/output (I/O) virtualization (SR-IOV) and a second agent unit supporting Virtio, and the first agent unit and the second agent unit each are an agent of a function unit in a network adapter such that, a virtual machine in the computer device may use an SR-IOV technology or a Virtio technology, and does not configure two sets of independent resource pools to separately support corresponding virtualization technologies, to implement normalization of the resource pools. In addition, the intermediate device implements hardware offloading of Virtio protocol packet forwarding using hardware.

公开(公告)号：US20230082069A1

公开(公告)日：2023-03-16

申请号：US17990942

申请日：2022-11-21

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Rongyu Yang ,  Yumin Wu ,  Tianchi Hu ,  Tao Li

IPC: H04L45/24 ,  H04L49/253

Abstract: In a data processing method, a timeout aggregation node of a cluster obtains first data that is partial aggregated data in a data-intensive computing task. The first data carries a first identifier of a timeout node indicating that a timeout occurs on the timeout node. The timeout aggregation node obtains second data of the timeout node based on the first identifier, where the second data is to-be-aggregated data sent by the timeout node. The timeout aggregation node aggregates the first data and the second data according to a preset rule to obtain third data that is complete aggregated data. The timeout aggregation node then notifies each computing node in the cluster of the third data.

公开(公告)号：US08990460B2

公开(公告)日：2015-03-24

申请号：US13707209

申请日：2012-12-06

Applicant: Huawei Technologies Co., Ltd.

Inventor： Sheng Chang ,  Rongyu Yang ,  Xinyu Hou

IPC: G06F13/36 ,  G06F13/40 ,  G06F15/17 ,  G06F13/42

CPC classification number: G06F13/40 ,  G06F13/4059 ,  G06F13/4265 ,  G06F13/4282 ,  G06F15/17 ,  G06F2213/0038 ,  G06F2213/3852

Abstract: The present disclosure provides a CPU interconnect device, the CPU interconnect device connects with a first CPU, which includes a quick path interconnect QPI interface and a serial deserial SerDes interface, the quick path interconnect QPI interface receives serial QPI data sent from a CPU, converts the received serial QPI data into a parallel QPI data, and outputs the parallel QPI data to the serial deserial SerDes interface; the serial deserial SerDes interface converts the parallel QPI data output by the QPI interface into a high-speed serial SerDes data and then send the high-speed serial SerDes data to another CPU interconnect device connected with another CPU. The defects of poor scalability, long data transmission delay, and a high cost of an existing interconnect system among CPUs can be solved.

Abstract translation: 本公开提供了一种CPU互连设备，CPU互连设备与包括快速路径互连QPI接口和串行解串联SerDes接口的第一CPU连接，快速路径互连QPI接口接收从CPU发送的串行QPI数据， 将接收到的串行QPI数据转换为并行QPI数据，并将并行QPI数据输出到串联解耦SerDes接口; 串行串行SerDes接口将QPI接口输出的并行QPI数据转换为高速串行SerDes数据，然后将高速串行SerDes数据发送到与另一个CPU连接的另一个CPU互连设备。 可以解决CPU之间的可扩展性差，长数据传输延迟以及现有互连系统成本高的缺陷。

公开(公告)号：US20150026527A1

公开(公告)日：2015-01-22

申请号：US14502326

申请日：2014-09-30

Applicant: Huawei Technologies Co., Ltd.

Inventor： Xinyu Hou ,  Sheng Chang ,  Rongyu Yang ,  Guang Lu

IPC: G06F11/07 ,  G06F11/263 ,  H04L1/08

CPC classification number: H04L1/24 ,  G06F11/076 ,  G06F11/263 ,  H04L1/0045 ,  H04L1/0061 ,  H04L1/08 ,  H04L1/1635 ,  H04L1/18 ,  H04L1/1825 ,  H04L1/1874 ,  H04L1/20 ,  H04L1/203 ,  H04L1/244

Abstract: A data transmission method, device and system to improve reliability of a data link. When the sender side detects erroneous data, the erroneous data is discarded and a data retransmission request is sent to the sender side to ensure correctness of received data and improve reliability of the data link; and, when the sender side detects the erroneous data and a bit error rate is greater than a preset bit error rate threshold, the data link gets into auto recovery, and data transmission is resumed after the recovery succeeds, thereby avoiding an excessively high bit error rate, preventing an excessively high probability of omitted checks (the higher the bit error rate is, the higher probability of omitted checks is), and further improving reliability of the data link.

Abstract translation: 一种提高数据链路可靠性的数据传输方法，设备和系统。 当发送方检测到错误数据时，丢弃错误数据，并向发送方发送数据重发请求，以确保接收到的数据的正确性并提高数据链路的可靠性; 并且当发送方检测到错误数据并且误码率大于预设误码率阈值时，数据链路进入自动恢复，并且在恢复成功之后恢复数据传输，从而避免了过高的位错误 速率，防止忽略检查的概率过高（误码率越高，省略检查的概率越高），并进一步提高数据链路的可靠性。

公开(公告)号：US08909979B2

公开(公告)日：2014-12-09

申请号：US13707188

申请日：2012-12-06

Applicant: Huawei Technologies Co., Ltd.

Inventor： Sheng Chang ,  Haibin Wang ,  Jie Zhang ,  Rongyu Yang ,  Xinyu Hou

IPC: G06F11/00 ,  G06F11/20 ,  G06F11/07 ,  G06F11/14

CPC classification number: G06F11/2005 ,  G06F11/0724 ,  G06F11/0745 ,  G06F11/0784 ,  G06F11/1443

Abstract: A system for implementing interconnection fault tolerance between CPUs, a first CPU and a second CPU implements interconnection through a first CPU interconnect device and a second CPU interconnect device. The system adds a data channel between a first SerDes interface of the first CPU interconnect device and a second SerDes interface of the second CPU interconnect device, and transmits link connection state information and a link control signal through the added data channel. The system monitors a link state of any one link in a CPU interconnection system, transmits the link state through the added data channel, recovers any one of the connection links when determining whether any one of the first connection link, the second connection link and the third connection link is faulty.

Abstract translation: 用于实现CPU之间的互连容错的系统，第一CPU和第二CPU通过第一CPU互连设备和第二CPU互连设备实现互连。 该系统在第一CPU互连设备的第一SerDes接口和第二CPU互连设备的第二SerDes接口之间添加数据信道，并通过添加的数据信道发送链路连接状态信息和链路控制信号。 系统监视CPU互连系统中任一链路的链路状态，通过添加的数据信道发送链路状态，在确定第一连接链路，第二连接链路和 第三连接链路故障。

公开(公告)号：US20130103875A1

公开(公告)日：2013-04-25

申请号：US13707209

申请日：2012-12-06

Applicant: Huawei Technologies Co., Ltd.

Inventor： Sheng Chang ,  Rongyu Yang ,  Xinyu Hou

IPC: G06F13/40

CPC classification number: G06F13/40 ,  G06F13/4059 ,  G06F13/4265 ,  G06F13/4282 ,  G06F15/17 ,  G06F2213/0038 ,  G06F2213/3852

Abstract: The present disclosure provides a CPU interconnect device, the CPU interconnect device connects with a first CPU, which includes a quick path interconnect QPI interface and a serial deserial SerDes interface, the quick path interconnect QPI interface receives serial QPI data sent from a CPU, converts the received serial QPI data into a parallel QPI data, and outputs the parallel QPI data to the serial deserial SerDes interface; the serial deserial SerDes interface converts the parallel QPI data output by the QPI interface into a high-speed serial SerDes data and then send the high-speed serial SerDes data to another CPU interconnect device connected with another CPU. The defects of poor scalability, long data transmission delay, and a high cost of an existing interconnect system among CPUs can be solved.

Abstract translation: 本公开提供了一种CPU互连设备，CPU互连设备与包括快速路径互连QPI接口和串行解串联SerDes接口的第一CPU连接，快速路径互连QPI接口接收从CPU发送的串行QPI数据，转换 将接收到的串行QPI数据转换为并行QPI数据，并将并行QPI数据输出到串联解耦SerDes接口; 串行串行SerDes接口将QPI接口输出的并行QPI数据转换为高速串行SerDes数据，然后将高速串行SerDes数据发送到与另一个CPU连接的另一个CPU互连设备。 可以解决CPU之间的可扩展性差，长数据传输延迟以及现有互连系统成本高的缺陷。