公开(公告)号：US10152420B2

公开(公告)日：2018-12-11

申请号：US15637805

申请日：2017-06-29

Applicant: Huawei Technologies Co., Ltd.

Inventor： Hengchao Xin

IPC: G06F12/08 ,  G06F12/0862 ,  G06F12/0875 ,  G06F12/0864 ,  G06F12/0895 ,  G06F12/126 ,  G06F12/0855

Abstract: A multi-way set associative cache and a processing method thereof, where the cache includes M pipelines, a controller, and a data memory, where any one of the pipelines includes an arbitration circuit, a tag memory, and a determining circuit, where the arbitration circuit receives at least one lookup request at an Nth moment, and determines a first lookup request among the at least one lookup request, the tag memory looks up locally stored tag information according to a first index address in order to acquire at least one target tag address corresponding to the first index address, the determining circuit determines whether an address that matches a first tag address exists in the at least one target tag address, and the controller sends the first lookup request to a next-level device or other pipelines for processing when the address that matches the first tag address does not exist.

公开(公告)号：US20170270984A1

公开(公告)日：2017-09-21

申请号：US15464670

申请日：2017-03-21

Applicant: Huawei Technologies Co., Ltd.

Inventor： Hengchao Xin

IPC: G11C7/22 ,  G11C7/10

CPC classification number: G11C7/222 ,  G06F5/06 ,  G11C7/10 ,  H04L7/0012

Abstract: A data reading circuit including a phase difference determining module, a time delay detection module, and a reading control module, and the phase difference determining module is connected to the echo clock signal and a clock signal of the second clock domain. The phase difference determining module is configured to determine a phase difference between the echo clock signal and the clock signal of the second clock domain; the time delay detection module is configured to detect a time delay value in transmission of data from a buffer to a flip-flop; and the reading control module is configured to determine, according to the phase difference and the time delay value, a triggering edge, at which the flip-flop can read data output by the buffer, of the clock signal of the second clock domain.