公开(公告)号：US10135758B2

公开(公告)日：2018-11-20

申请号：US15461666

申请日：2017-03-17

Applicant: Huawei Technologies Co., Ltd.

Inventor： Hengchao Xin ,  Han Lin ,  Jing Xia

IPC: H04L12/935 ,  H04L12/26 ,  H04L12/933

Abstract: A chip is provided, where the chip is formed by packaging at least two dies, and the at least two dies form at least one die group. The die group includes a first die and a second die. A first processing unit and n groups of ports are disposed on the first die, and a second processing unit and m groups of ports are disposed on the second die. The first processing unit is configured to: switch at least one group of first type ports in the n groups of ports from input to output and switch a second type port that is in the m groups of ports and that is coupled to each group of the first type ports from output to input.

公开(公告)号：US20170300417A1

公开(公告)日：2017-10-19

申请号：US15637805

申请日：2017-06-29

Applicant: Huawei Technologies Co., Ltd.

Inventor： Hengchao Xin

IPC: G06F12/08 ,  G06F12/12

CPC classification number: G06F12/0862 ,  G06F12/08 ,  G06F12/0855 ,  G06F12/0864 ,  G06F12/0875 ,  G06F12/0895 ,  G06F12/126 ,  G06F2212/1016 ,  G06F2212/6022

Abstract: A multi-way set associative cache and a processing method thereof, where the cache includes M pipelines, a controller, and a data memory, where any one of the pipelines includes an arbitration circuit, a tag memory, and a determining circuit, where the arbitration circuit receives at least one lookup request at an Nth moment, and determines a first lookup request among the at least one lookup request, the tag memory looks up locally stored tag information according to a first index address in order to acquire at least one target tag address corresponding to the first index address, the determining circuit determines whether an address that matches a first tag address exists in the at least one target tag address, and the controller sends the first lookup request to a next-level device or other pipelines for processing when the address that matches the first tag address does not exist.

公开(公告)号：US20240089143A1

公开(公告)日：2024-03-14

申请号：US18510972

申请日：2023-11-16

Applicant: Huawei Technologies Co., Ltd.

Inventor： Jing Xia ,  Nan Duan ,  Chunxiao Cai ,  Hengchao Xin

IPC: H04L12/40

CPC classification number: H04L12/40 ,  H04L2012/40273

Abstract: This disclosure relates to a chip, an electronic device, a transportation vehicle, and a method for generating a control signal. The chip includes a mesh bus and a ring bus. The mesh bus is coupled to each sensor to receive and transmit perception data. The ring bus is coupled to a processor and the mesh bus. The processor receives different types of perception data from different sensors such as a camera and a lidar, and fuses the data to generate a control signal for controlling an execution apparatus.

公开(公告)号：US20240028528A1

公开(公告)日：2024-01-25

申请号：US18477110

申请日：2023-09-28

Applicant: Huawei Technologies Co., Ltd.

Inventor： Jing Xia ,  Hengchao Xin ,  Zhuonan Li ,  Sirui Yuan

IPC: G06F13/16

CPC classification number: G06F13/1668 ,  G06F13/1663 ,  G06F13/1642

Abstract: This application discloses a read/write operation execution method and a SoC chip. The read/write operation execution method includes: A first node receives a first message and a second message from a second node, where the first message is for requesting to perform a read/write operation on a first address managed by a third node, the second message is for requesting to perform a read/write operation on a second address managed by the third node, an execution sequence constraint of the read/write operation of the second node is stricter than an execution sequence constraint of the read/write operation of the third node; the first node obtains operation permission of the first address and operation permission of the second address from the third node; and the first node performs read/write operations on the first address and the second address.

公开(公告)号：US09824731B2

公开(公告)日：2017-11-21

申请号：US15464670

申请日：2017-03-21

Applicant: Huawei Technologies Co., Ltd.

Inventor： Hengchao Xin

IPC: G11C7/22 ,  G11C7/10

CPC classification number: G11C7/222 ,  G06F5/06 ,  G11C7/10 ,  H04L7/0012

Abstract: A data reading circuit including a phase difference determining module, a time delay detection module, and a reading control module, and the phase difference determining module is connected to the echo clock signal and a clock signal of the second clock domain. The phase difference determining module is configured to determine a phase difference between the echo clock signal and the clock signal of the second clock domain; the time delay detection module is configured to detect a time delay value in transmission of data from a buffer to a flip-flop; and the reading control module is configured to determine, according to the phase difference and the time delay value, a triggering edge, at which the flip-flop can read data output by the buffer, of the clock signal of the second clock domain.

公开(公告)号：US11789866B2

公开(公告)日：2023-10-17

申请号：US17749612

申请日：2022-05-20

Applicant: Huawei Technologies Co., Ltd.

Inventor： Wenyu Wu ,  Jing Xia ,  Hengchao Xin

IPC: G06F12/00 ,  G06F12/0802

CPC classification number: G06F12/0802 ,  G06F2212/60

Abstract: A method for processing a non-cache data write request includes a cache receiving a first non-cache data write request from a first processor, and sending the first non-cache data write request to a node, where the first non-cache data write request includes a first address. If the cache determines that the first address is stored in the cache, the cache obtains first data corresponding to the first non-cache data write request from the first processor. When receiving a first data buffer identifier from the node, the cache sends the first data to the node. After receiving the first non-cache data write request, if the cache determines that the first address is locally stored, the cache may obtain the first data from the processor. After receiving the first data buffer identifier, the cache may send the first data to the node.

公开(公告)号：US20210149804A1

公开(公告)日：2021-05-20

申请号：US17162287

申请日：2021-01-29

Applicant: Huawei Technologies Co., Ltd.

Inventor： Hengchao Xin ,  Jing Xia ,  Hongyi Zeng ,  Zhirui Chen

IPC: G06F12/0846 ,  G06F12/02 ,  G06F12/06 ,  G06F13/16

Abstract: A memory interleaving method includes dividing an access capacity into P partial access capacities based on N pieces of configuration information, where the P partial access capacities have a same size, the N pieces of configuration information are of N memory channels, where one of the N pieces of configuration information corresponds to one memory channel of the N memory channels, each of the N configuration information indicates a quantity of first partial access capacities of the P partial access capacities correspond to a first memory channel, and two partial access capacities correspond to a second memory channel, where a total quantity of memory channels is N, and N is an integer greater than or equal to 2, and mapping the P partial access capacities to the N memory channels.

公开(公告)号：US20170272385A1

公开(公告)日：2017-09-21

申请号：US15461666

申请日：2017-03-17

Applicant: Huawei Technologies Co., Ltd.

Inventor： Hengchao Xin ,  Han Lin ,  Jing Xia

IPC: H04L12/935 ,  H04L12/26

CPC classification number: H04L49/30 ,  H04L43/08 ,  H04L49/109

Abstract: A chip is provided, where the chip is formed by packaging at least two dies, and the at least two dies form at least one die group. The die group includes a first die and a second die. A first processing unit and n groups of ports are disposed on the first die, and a second processing unit and m groups of ports are disposed on the second die. The first processing unit is configured to: switch at least one group of first type ports in the n groups of ports from input to output and switch a second type port that is in the m groups of ports and that is coupled to each group of the first type ports from output to input.

公开(公告)号：US20220276960A1

公开(公告)日：2022-09-01

申请号：US17749612

申请日：2022-05-20

Applicant: Huawei Technologies Co., Ltd.

Inventor： Wenyu Wu ,  Jing Xia ,  Hengchao Xin

IPC: G06F12/0802

Abstract: A method for processing a non-cache data write request, a cache, and a node are provided. The method includes: A cache receives a first non-cache data write request from a first processor, and sends the first non-cache data write request to a node, where the first non-cache data write request includes a first address. If the cache determines that the first address is stored in the cache, the cache obtains first data corresponding to the first non-cache data write request from the first processor. When receiving a first data buffer identifier from the node, the cache sends the first data to the node. After receiving the first non-cache data write request, if the cache determines that the first address is locally stored, the cache may obtain the first data from the processor. After receiving the first data buffer identifier, the cache may send the first data to the node.

公开(公告)号：US11037615B2

公开(公告)日：2021-06-15

申请号：US16932255

申请日：2020-07-17

Applicant: Huawei Technologies Co., Ltd.

Inventor： Hengchao Xin ,  Jing Xia ,  Yining Li ,  Zhenxi Tu

IPC: G11C11/406

Abstract: A refresh processing method, apparatus, and system, and memory controllers are provided, to improve memory access efficiency. The refresh processing apparatus includes a plurality of memory controllers that are in one-to-one correspondence with a plurality of memory spaces. Any first memory controller in the plurality of memory controllers is configured to: receive N first indication signals and N second indication signals that are output by N memory controllers other than the first memory controller, where N is greater than or equal to 1; and determine a refresh policy of a first memory space based on at least one of the following information: the N first indication signals, the N second indication signals, and refresh indication information of the first memory space.