公开(公告)号：US06252441B1

公开(公告)日：2001-06-26

申请号：US09585443

申请日：2000-06-02

Applicant: Hyong-yong Lee ,  Sang-chul Kim

Inventor： Hyong-yong Lee ,  Sang-chul Kim

IPC: H03L700

CPC classification number: G11C7/1093 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/22

Abstract: A synchronous data sampling circuit and method are provided by which it is possible to sample four data items during one cycle of a clock signal. In the synchronous data sampling circuit a first pulse signal generator receives the clock signal and generates a first pulse signal during a logic “low” interval of the clock signal. A second pulse signal generator receives the clock signal and generates a second pulse signal during a logic “high” interval of the clock signal. A first sampling unit samples first data input through the input port and outputs the sampled first data to the output port in response to the falling edge of the clock signal. A second sampling unit samples second data input through the input port and outputs the sampled second data to the output port in response to a rising or falling edge of the first pulse signal. A third sampling unit samples third data input through the input port and outputs the sampled third data to the output port in response to the rising edge of the clock signal. A fourth sampling unit samples fourth data input through the input port and outputs the sampled fourth data to the output port in response to the rising or falling edge of the second pulse signal. As a result, four data items are sampled during one cycle of the clock signal, doubling the data sampling efficiency, as compared to the data sampling efficiency of a conventional dual data rate (DDR) method.

Abstract translation: 提供了一种同步数据采样电路和方法，通过该方法可以在时钟信号的一个周期期间对四个数据项进行采样。 在同步数据采样电路中，第一脉冲信号发生器在时钟信号的逻辑“低”间隔期间接收时钟信号并产生第一脉冲信号。 第二脉冲信号发生器在时钟信号的逻辑“高”间隔期间接收时钟信号并产生第二脉冲信号。 第一采样单元对通过输入端口输入的第一数据进行采样，并响应于时钟信号的下降沿将采样的第一数据输出到输出端口。 第二采样单元通过输入端口采样第二数据输入，并响应于第一脉冲信号的上升沿或下降沿将采样的第二数据输出到输出端口。 第三采样单元对通过输入端口输入的第三数据进行采样，并响应于时钟信号的上升沿将采样的第三数据输出到输出端口。 第四采样单元对通过输入端口输入的第四数据进行采样，并响应于第二脉冲信号的上升沿或下降沿将采样的第四数据输出到输出端口。 结果，与传统双数据速率（DDR）方法的数据采样效率相比，在时钟信号的一个周期期间对四个数据项进行采样，使数据采样效率翻倍。