公开(公告)号：US20140269999A1

公开(公告)日：2014-09-18

申请号：US13839557

申请日：2013-03-15

Applicant: INNOPHASE, INC.

Inventor： Jian Cui ,  Sara Munoz Hermoso ,  Yang Xu

IPC: H04L27/227

CPC classification number: H04L27/389 ,  H04L27/3818

Abstract: A method of generating inphase and quadrature signals from a polar receiver providing a phase derivative signal and an envelope magnitude signal comprising receiving an estimated phase derivative signal; generating an estimated phase signal; mapping the estimated phase signal to an angular value; converting the estimated phase signal to an inphase signal and a quadrature signal based on the angular value; and, providing the inphase signal and quadrature signal to a demodulation circuit.

Abstract translation: 一种从提供相位导数信号和包络幅度信号的极坐标接收机产生同相和正交信号的方法，包括接收估计的相位导数信号; 产生估计相位信号; 将估计的相位信号映射到角度值; 基于角度值将所估计的相位信号转换为同相信号和正交信号; 并向解调电路提供同相信号和正交信号。

公开(公告)号：US20140266454A1

公开(公告)日：2014-09-18

申请号：US13839462

申请日：2013-03-15

Applicant: INNOPHASE, INC.

Inventor： Nicolo Testi ,  Xi Li ,  Xuejun Zhang ,  Yang Xu

IPC: H03G3/00

CPC classification number: H03G3/008 ,  H03G1/0029 ,  H03G1/0088 ,  H03G5/14 ,  H03G5/24

Abstract: A low noise amplifier including a variable gain amplifier stage configured to accept an input signal and to provide a load driving signal; a tunable bandpass filter connected as a load to the variable gain amplifier stage, wherein the bandpass filter includes a cross-coupled transistor pair, and at least one cross-coupled compensation transistor pair biased in a subthreshold region configured to add a transconductance component when the load driving signal is of a magnitude large enough to decreases a transconductance of the cross-coupled transistor pair; and, a controller circuit configured to tune the bandpass filter. The filter can be tuned in respect to the frequency and the quality factor Q.

Abstract translation: 一种低噪声放大器，包括可变增益放大器级，其被配置为接受输入信号并提供负载驱动信号; 作为负载连接到可变增益放大器级的可调谐带通滤波器，其中所述带通滤波器包括交叉耦合晶体管对，以及偏置在亚阈值区域中的至少一个交叉耦合补偿晶体管对，其配置成当所述跨导分量 负载驱动信号的幅度足够大以减小交叉耦合晶体管对的跨导; 以及配置为调谐带通滤波器的控制器电路。 滤波器可以根据频率和质量因子Q进行调整。

公开(公告)号：US08542779B2

公开(公告)日：2013-09-24

申请号：US13754819

申请日：2013-01-30

Applicant: Innophase Inc.

Inventor： Yang Xu

IPC: H03D3/18 ,  H03D3/24

CPC classification number: H04L27/2272 ,  H04L27/2071 ,  H04L27/22

Abstract: A receiver is described. The receiver includes a first injection-locked oscillator having a first input configured to receive a BPSK signal and a second input configured to receive a first frequency reference. The receiver also includes a second injection-locked oscillator having a third input configured to receive the BPSK signal and a fourth input configured to receive a second frequency reference. Further, the receiver includes a first phase-locked loop coupled with the second input of the first injection-locked oscillator. The first phase-locked loop is configured to generate the first frequency reference. And, a second phase-locked loop is coupled with the fourth input of the second injection-locked oscillator. The second phase-locked loop is configured to generate the second frequency reference.

Abstract translation: 描述接收机。 接收机包括第一注入锁定振荡器，其具有被配置为接收BPSK信号的第一输入和被配置为接收第一频率参考的第二输入。 接收机还包括第二注入锁定振荡器，其具有被配置为接收BPSK信号的第三输入和被配置为接收第二频率参考的第四输入。 此外，接收机包括与第一注入锁定振荡器的第二输入耦合的第一锁相环。 第一锁相环被配置为产生第一频率参考。 并且，第二锁相环与第二注入锁定振荡器的第四输入耦合。 第二锁相环被配置为产生第二频率参考。

公开(公告)号：US20130195157A1

公开(公告)日：2013-08-01

申请号：US13754853

申请日：2013-01-30

Applicant: Innophase Inc.

Inventor： Yang Xu

IPC: H04L27/20

CPC classification number: H04L27/2272 ,  H04L27/2071 ,  H04L27/22

Abstract: A transceiver is described. The transceiver includes a first injection-locked oscillator and a second injection-locked oscillator. The transceiver also includes a first phase-locked loop coupled with the first injection-locked oscillator. The first phase-locked loop is configured to generate a first frequency reference. Further, the transceiver includes a second phase-locked loop coupled the second injection-locked oscillator. The second phase-locked loop is configured to generate a second frequency reference. The transceiver includes a mixer configured to receive the first phase-locked loop output and configured to receive said second injection-locked oscillator output. The mixer is also configured to generate a carrier frequency signal based on the first injection-locked oscillator output and the second injection-locked oscillator output. And, the transceiver includes a modulator configured to receive said carrier frequency signal.

Abstract translation: 描述收发器。 收发器包括第一注入锁定振荡器和第二注入锁定振荡器。 收发器还包括与第一注入锁定振荡器耦合的第一锁相环。 第一锁相环被配置为产生第一频率参考。 此外，收发器包括耦合第二注入锁定振荡器的第二锁相环。 第二锁相环被配置为产生第二频率参考。 收发器包括配置成接收第一锁相环输出并被配置为接收所述第二注入锁定振荡器输出的混频器。 混频器还被配置为基于第一注入锁定振荡器输出和第二注入锁定振荡器输出产生载波频率信号。 并且，收发器包括被配置为接收所述载波频率信号的调制器。

公开(公告)号：US12244066B2

公开(公告)日：2025-03-04

申请号：US17772861

申请日：2020-10-28

Applicant: Innophase, Inc.

Inventor： Jeffrey Shamblin ,  Yang Xu ,  Claudio Anzil

IPC: H01Q21/06 ,  H01Q5/307 ,  H01Q9/16 ,  H01Q13/00

Abstract: A dual-band, tri-band, or higher-order multi-band array of antenna elements, with each element, or subsets of elements, connected to multiple radios at each antenna port. In one embodiment, an array comprises a 128 element Massive MIMO array having 64 horizontally-polarized (H-pol) and 64 vertically-polarized (V-pol) elements configured to provide dual polarization capability over multiple bands to accommodate highly-configurable simultaneous 4G and 5G operation.

公开(公告)号：US20240007157A1

公开(公告)日：2024-01-04

申请号：US18346178

申请日：2023-06-30

Applicant: Innophase, Inc. ,  Parallel Wireless, Inc.

Inventor： Yang Xu ,  Steven Paul Papa

IPC: H04B7/06

CPC classification number: H04B7/0617

Abstract: Digital Beam-Formed Data Packet Communication Across Serially-Connected Transceivers by receiving modulated RF signals at a plurality of signal ports of each transceiver IC in a subarray of serially connected transceiver ICs and generating one or more frequency domain digital data packets of subcarrier IQ data associated with each signal port by demodulating each modulated RF signal from each signal port using an FFT processor within the respective transceiver ICs, and forming a plurality of combined frequency domain digital data packets from the transceiver ICs using a set of serial data links between the transceiver ICs of the subarray of serially connected transceiver ICs; and transmitting the plurality of combined frequency domain digital data packets from the subarray of transceiver ICs to a beamformer processor.

公开(公告)号：US20240007152A1

公开(公告)日：2024-01-04

申请号：US18346191

申请日：2023-06-30

Applicant: Innophase, Inc.

Inventor： Yang Xu ,  Nicolo Testi ,  Jongheon Kim

IPC: H04B7/0426 ,  H04L27/26

CPC classification number: H04B7/043 ,  H04L27/26025

Abstract: Transceiver integrated circuit suitable for distributed placement across an active antenna unit. ICs with two serial data ports configured to transmit and receive aggregated signal-port IQ data packets with adjacent ICs within a subarray of ICs, or to a beamformer processor. A packet header inspection circuit may identify aggregated signal-port IQ data packets for local processing, and identify received aggregated signal-port IQ data packets for processing by another device.

公开(公告)号：US20230129253A1

公开(公告)日：2023-04-27

申请号：US18069118

申请日：2022-12-20

Applicant: Innophase, Inc.

Inventor： Yang Xu ,  Jeffrey Shamblin

IPC: H01Q21/22 ,  H04B1/401 ,  H04B1/44 ,  H04B7/06

Abstract: A configurable array having a plurality of antenna elements arranged in at least four adjacent groups of array elements on a panel array, the first group of elements having an inter-element spacing based on a transmit signal wavelength, a second group of elements having an inter-element spacing based on a receive signal wavelength, and a third and fourth group of elements having an inter-element spacing based on a wavelength between the transmit signal wavelength and the receive signal wavelength.

公开(公告)号：US11159187B2

公开(公告)日：2021-10-26

申请号：US16286548

申请日：2019-02-26

Applicant: Parallel Wireless, Inc. ,  Innophase, Inc.

Inventor： Steven Paul Papa ,  Yang Xu

IPC: H04B1/04 ,  H04L5/14 ,  H01Q1/24 ,  H04B7/0452

Abstract: A microcomponent massive MIMO array is presented. The microcomponent massive array includes a general purpose processor and an integrated power amplifier and transmitter device including a software defined radio (SDR) and a plurality of polar power amplifiers (PAs) disposed on a single integrated circuit, wherein the integrated power amplifier and transmitter device is in communication with the general purpose processor. The microcomponent massive MIMO array further includes an antenna array in communication with the integrated power amplifier and transmitter device.

公开(公告)号：US11095296B2

公开(公告)日：2021-08-17

申请号：US16890771

申请日：2020-06-02

Applicant: Innophase, Inc.

Inventor： Sara Munoz Hermoso ,  Per Konradsson ,  Yang Xu

IPC: H03L7/099 ,  H03B5/12

Abstract: An example method in accordance with some embodiments includes: determining an output frequency control word (FCW) having a plurality of bits, the output FCW being configured to control an oscillator, the oscillator including a plurality of capacitor banks, the plurality of capacitor banks respectively corresponding to the plurality of bits of the output FCW; storing the output FCW in a clocked delay cell; providing an input clock to the clocked delay cell, wherein the input clock is provided to delay the output FCW by an amount of delay; and, in accordance with the input clock, releasing the delayed output FCW from the clocked delay cell, and respectively applying the plurality of bits of the delayed output FCW to the plurality of capacitor banks of the oscillator.