公开(公告)号：US20190215142A1

公开(公告)日：2019-07-11

申请号：US16352180

申请日：2019-03-13

申请人： Cavium, LLC

发明人： Scott E. Meninger

IPC分类号： H04L7/00 ,  H04L1/00 ,  H03L7/08 ,  H03L7/00 ,  H04L27/227

CPC分类号： H04L7/0008 ,  G06F1/06 ,  G06F1/10 ,  H03L7/00 ,  H03L7/08 ,  H03L7/1976 ,  H03L7/23 ,  H03M9/00 ,  H04J3/0685 ,  H04L1/0065 ,  H04L27/2272

摘要： A circuit and method enables multiple serializer/deserializer (SerDes) data lanes of a physical layer device (PHY) to operate across a broad range of diversified data rates that are independent from lane to lane. The multiple SerDes data lanes may operate at data rates independent from one another. A single low frequency clock is input to the PHY. A frequency of the single low frequency clock is increased via a common integer-N phase-locked loop (PLL) on the PHY to produce a higher frequency clock. Each of the SerDes data lanes is operated, independently, as a fractional-N PLL that employs the higher frequency clock. Use of the common integer-N PLL enables modulation noise of the fractional-N PLLs to be suppressed by moving the modulation noise to higher frequencies where a level of the modulation noise is filtered, avoiding use of high risk noise cancellation techniques.

公开(公告)号：US10057051B2

公开(公告)日：2018-08-21

申请号：US14983830

申请日：2015-12-30

申请人： Silicon Laboratories Inc.

发明人： Yunteng Huang

IPC分类号： H04L7/033 ,  H04L27/227 ,  H04J3/06 ,  H03L7/093 ,  H03L7/08 ,  H03L7/081 ,  H03L7/085 ,  H03L7/099

CPC分类号： H04L7/0332 ,  H03L7/0805 ,  H03L7/081 ,  H03L7/085 ,  H03L7/093 ,  H03L7/0991 ,  H03L7/0994 ,  H04J3/0661 ,  H04L7/002 ,  H04L27/2272

摘要： A more cost effective wander jitter filter utilizes an excursion detector that receives a timing difference between a first signal and a second signal and supplies a first adjustment amount if a magnitude of the timing difference is above a predetermined threshold and otherwise supplies a second adjustment amount of zero. A summing circuit adjusts a magnitude of the timing difference by the first or second adjustment amount. A loop filter receives the summing circuit output and controls an oscillator. The excursion detector output (first adjustment value or zero according to the magnitude of the timing difference) is low pass filtered and the low pass filtered is reintroduced into the oscillator output or the feedback loop. The excursion detector output is accumulated and used to adjust a phase of the feedback signal from the oscillator.

公开(公告)号：US09924206B2

公开(公告)日：2018-03-20

申请号：US15653340

申请日：2017-07-18

申请人： LG Electronics Inc.

发明人： Jong Moon Kim ,  In Hwan Choi ,  Kook Yeon Kwak ,  Byoung Gill Kim ,  Won Gyu Song ,  Jin Woo Kim ,  Hyoung Gon Lee

IPC分类号： H04L27/00 ,  H04N21/235 ,  H04N5/455 ,  H04N21/438 ,  H04N21/2383 ,  H04L7/04 ,  H04L1/00 ,  H04N5/44 ,  H04L7/027 ,  H04L27/227 ,  H04L27/06

CPC分类号： H04N21/2353 ,  H04L1/006 ,  H04L1/0065 ,  H04L1/007 ,  H04L1/0071 ,  H04L7/027 ,  H04L7/042 ,  H04L27/066 ,  H04L27/2272 ,  H04N5/4401 ,  H04N5/455 ,  H04N21/2383 ,  H04N21/4382

摘要： A digital television (DTV) receiving system includes an information detector, a resampler, a timing recovery unit, and a carrier recovery unit. The information detector detects a known data sequence which is periodically inserted in a digital television (DTV) signal received from a DTV transmitting system. The resampler resamples the DTV signal at a predetermined resampling rate. The timing recovery unit performs timing recovery on the DTV signal by detecting a timing error from the resampled DTV signal using the detected known data sequence. The carrier recovery unit performs carrier recovery on the resampled DTV signal by estimating a frequency offset value of the resampled DTV signal using the detected known data sequence.

公开(公告)号：US09769597B2

公开(公告)日：2017-09-19

申请号：US15089892

申请日：2016-04-04

申请人： Telink Semiconductor (Shanghai) Co., LTD.

发明人： Haipeng Jin ,  Wenjun Sheng ,  Mingjian Zheng

IPC分类号： H04M1/00 ,  H04W4/00 ,  H04L27/227 ,  H04L27/12 ,  H04L27/20 ,  H04B1/00 ,  H04L25/02 ,  H04W88/06 ,  H04B1/04

CPC分类号： H04W4/80 ,  H03F3/24 ,  H04B1/0014 ,  H04B2001/0408 ,  H04L25/02 ,  H04L27/12 ,  H04L27/20 ,  H04L27/2272 ,  H04W88/06 ,  Y02D70/00

摘要： The present disclosure relates to a ZigBee/Bluetooth dual-mode radio frequency transceiver architecture, in which, a dual-mode baseband and firmware determines hardware parameter of a receiving module or sending module based on a first mode or a second mode; a radio frequency front-end module is used for receiving or sending a first mode signal or a second mode signal; a receiving module is used for converting the first mode signal received by the radio frequency front-end module into a first mode baseband digital signal, or converting the second mode signal received by the radio frequency front-end module into a second mode baseband digital signal and outputting the first mode baseband digital signal or the second mode baseband digital signal to the dual-mode baseband and firmware; a sending module is used for converting the first mode baseband digital signal outputted by dual-mode baseband and firmware into the first mode signal.

公开(公告)号：US09705668B2

公开(公告)日：2017-07-11

申请号：US14725053

申请日：2015-05-29

申请人： Silicon Laboratories Inc.

发明人： Yunteng Huang

IPC分类号： H03D3/24 ,  H04L7/033 ,  H04L27/227

CPC分类号： H04L7/0332 ,  H03L7/0807 ,  H03L7/148 ,  H04J3/0614 ,  H04L27/2272

摘要： A gap detector detects when a phase difference between a feedback signal and a clock signal is larger than a gap threshold. If the phase difference is larger than the gap threshold, then the phase difference is modified by subtracting a gap value from the phase difference. If the phase difference is less than the threshold, the phase difference is not modified. A loop filter receives and filters the modified or unmodified phase difference and controls an oscillator. An accumulator circuit accumulates the modified phase difference and supplies a phase adjust signal. A low pass filter receives the phase adjust signal and supplies a filtered phase adjust signal that is used to slowly adjust the output of the oscillator.

公开(公告)号：US20170012676A1

公开(公告)日：2017-01-12

申请号：US15204310

申请日：2016-07-07

申请人： Commissariat A L'Energie Atomique et aux Energies Alternatives

发明人： Pierre COUROUVE ,  Jean-Baptiste DORE ,  Manuel PEZZIN

IPC分类号： H04B5/00 ,  H04L27/227

CPC分类号： H04B5/0062 ,  H03D3/007 ,  H03D3/04 ,  H04L27/2272 ,  H04L27/2278 ,  H04L27/233 ,  H04L27/3845

摘要： A quadrature demodulator not requiring analogue mixers. The demodulation is made using a first integrator and a second integrator which are controlled by square logic signals at twice the frequency of the carrier, the received signal being alternatively integrated by the first integrator and the second integrator over periods of time equal to a quarter period of time of the carrier frequency. The samples of the first and second integrators are sampled and subtracted from each other. The successive samples are combined in a first and a second combining module for providing in-phase and quadrature component samples. This demodulator can further be provided with a synchronization module IQ and a symbol synchronization module.

摘要翻译： 不需要模拟混频器的正交解调器。 使用由载波频率的两倍的平方逻辑信号控制的第一积分器和第二积分器进行解调，接收到的信号由等于四分之一周期的时间段由第一积分器和第二积分器交替地集成 的载波频率的时间。 对第一和​​第二积分器的样本进行采样并相减。 连续样本在第一和第二组合模块中组合以提供同相和正交分量样本。 该解调器还可以设置有同步模块IQ和符号同步模块。

公开(公告)号：US09231649B2

公开(公告)日：2016-01-05

申请号：US14546364

申请日：2014-11-18

申请人： Research & Business Foundation SUNGKYUNKWAN UNIVERSITY

发明人： Keun Hong Chae ,  Seok Ho Yoon

IPC分类号： H04B1/16 ,  H04B1/709 ,  H03L7/06 ,  H04L27/227 ,  H04B1/707 ,  H04L27/00 ,  H04J13/00 ,  G01S19/30 ,  G01S19/24

CPC分类号： H04B1/709 ,  G01S19/24 ,  G01S19/30 ,  H03L7/06 ,  H03L7/07 ,  H03L7/0812 ,  H03L7/093 ,  H03L7/0991 ,  H04B1/16 ,  H04B1/707 ,  H04J13/00 ,  H04L27/00 ,  H04L27/2272

摘要： A method of generating the correlation function of a TMBOC(6,1,4/33) signal according to the present invention includes generating a signal delayed based on a phase delay τ with respect to a signal pulse train of a TMBOC(6,1,4/33)-modulated received signal, generating 12 partial correlation functions by performing the autocorrelation operation of the received signal and the delayed signal with respect to a total time T(0≦t≦T) , generating a sub-correlation function by performing an elimination operation of sixth and seventh partial correlation functions, and generating a main correlation function by summing results obtained by performing elimination operations between the remaining 10 partial correlation functions, excluding the sixth and seventh early partial correlation functions from the 12 partial correlation functions, and the sub-correlation function. The elimination operation is an operation satisfying algebraic relations in which |A|+|B|−|A−B|=0 when real numbers A and B are AB≦0 and |A|+|B|−|A−B|>0 when the real numbers A and B are AB>0 .

摘要翻译： 根据本发明的产生TMBOC（6,1,4 / 33）信号的相关函数的方法包括：基于相对于TMBOC（6,1）的信号脉冲串的相位延迟τ产生延迟的信号 ，4/33）调制的接收信号，通过相对于总时间T（0＆amp; nlE; t＆nlE; T）执行接收信号和延迟信号的自相关操作来产生12个部分相关函数，通过 执行第六和第七部分相关函数的消除操作，并且通过对从12个部分相关函数中排除第六和第七早期部分相关函数之外的剩余的10个部分相关函数之间执行消除操作获得的结果求和得到主相关函数， 和子相关函数。 当实数A和B为AB＆nlE时，消除操作是满足代数关系的操作，其中| A | + | B | - | A-B | = 0; 0和| A | + | B | - | A-B | > 0，当实数A和B为AB> 0时。

公开(公告)号：US20150010113A1

公开(公告)日：2015-01-08

申请号：US14492427

申请日：2014-09-22

申请人： Renesas Electronics Corporation

发明人： Yutaka Igarashi ,  Yusaku Katsube

IPC分类号： H04L27/00 ,  H04B1/30 ,  H04L27/227

CPC分类号： H04L27/0002 ,  H04B1/006 ,  H04B1/30 ,  H04B1/406 ,  H04L27/2272

摘要： A semiconductor integrated circuit includes a first wireless access system reception unit including a first analog reception unit and a first digital reception unit, a voltage-controlled oscillator, a phase locked loop, and a digital interface. The first analog reception unit comprises a first reception mixer for down-converting an RF reception signal into a first analog reception signal and a first analog-digital converter for converting the first analog reception signal into a first digital reception signal. The first wireless access system reception unit, the voltage-controlled oscillator, and the phase locked loop enable switching from a reception operation for a first RF reception signal of a first system to a reception operation for a second RF reception signal of a second system.

摘要翻译： 半导体集成电路包括：第一无线接入系统接收单元，包括第一模拟接收单元和第一数字接收单元，压控振荡器，锁相环和数字接口。 第一模拟接收单元包括用于将RF接收信号下变频为第一模拟接收信号的第一接收混合器和用于将第一模拟接收信号转换为第一数字接收信号的第一模数转换器。 第一无线接入系统接收单元，压控振荡器和锁相环使得能够从第一系统的第一RF接收信号的接收操作切换到第二系统的第二RF接收信号的接收操作。

公开(公告)号：US08885773B2

公开(公告)日：2014-11-11

申请号：US13092880

申请日：2011-04-22

申请人： Choong Yul Cha ,  Kenneth K. O

发明人： Choong Yul Cha ,  Kenneth K. O

IPC分类号： H03D1/24 ,  H04L27/227 ,  H04L27/00

CPC分类号： H04L27/2272 ,  H04L2027/0028 ,  H04L2027/0055

摘要： An ultra low power radio receiver architecture based on phase locked loop is provided. Embodiments of an ultra low power radio receiver architecture based on phase locked loop can detect a complex modulated MSK signal with only a single path receiver chain. According to an embodiment of the present invention, the overall power consumption of the radio receiver in the present invention can be reduced by almost fifty percent compared to that of the conventional complex path radio receiver architecture. The radio receiver architecture of the invention is suitable for the ultra low power radio application such as wireless sensor networks (WSN).

摘要翻译： 提供了一种基于锁相环的超低功耗无线电接收机架构。 基于锁相环的超低功率无线电接收器架构的实施例可以仅使用单个路径接收器链来检测复数调制的MSK信号。 根据本发明的实施例，与传统的复杂路径无线电接收机架构相比，本发明中的无线电接收机的总功耗可以减少近百分之五十。 本发明的无线电接收机架构适用于诸如无线传感器网络（WSN）的超低功率无线电应用。

公开(公告)号：US08811541B2

公开(公告)日：2014-08-19

申请号：US13794699

申请日：2013-03-11

申请人： National Taiwan University

发明人： Yi-Lin Tsai ,  Jian-You Chen ,  Bang-Cyuan Wang ,  Tsung-Hsien Lin

IPC分类号： H03D3/00 ,  H04L27/227

CPC分类号： H04L27/2272 ,  H04L27/2071

摘要： A signal demodulation module is disclosed. The signal demodulation module includes an injection-locked oscillator, an envelope detector and a data slicer. The injection-locked oscillator has a central oscillating frequency equal to a frequency of a digital modulation signal received, and outputs a phase-locked oscillating signal which is in phase to the digital modulation signal. When input phase of the digital modulation signal changes, output phase of the injection-locked oscillator changes synchronously. The envelope detector is used for detecting an envelope line of the phase-locked oscillating signal and outputting an envelope signal accordingly. The data slicer is used for receiving the envelop signal and outputting a first digital signal according to a reference voltage and the envelop signal.

摘要翻译： 公开了一种信号解调模块。 信号解调模块包括注入锁定振荡器，包络检测器和数据限幅器。 注入锁定振荡器具有等于接收到的数字调制信号的频率的中心振荡频率，并且输出与数字调制信号同相的锁相振荡信号。 当数字调制信号的输入相位变化时，注入锁定振荡器的输出相位同步变化。 包络检测器用于检测锁相振荡信号的包络线，并相应地输出包络信号。 数据限幅器用于接收包络信号，并根据参考电压和包络信号输出第一数字信号。