公开(公告)号：US20240243715A1

公开(公告)日：2024-07-18

申请号：US18600593

申请日：2024-03-08

Applicant: CHIPSEA TECHNOLOGIES (SHENZHEN) CORP.

Inventor： Min CHEN ,  Peiteng CHEN

IPC: H03G1/00 ,  H03F3/45 ,  H03G3/00

CPC classification number: H03G1/0088 ,  H03F3/45475 ,  H03G3/001 ,  H03F2200/261

Abstract: A programmable gain amplifier includes a first-stage operational transconductance amplifier (OTA), a second-stage OTA, a capacitor module, a clock oscillation circuit, and a correction circuit. An input terminal of the second-stage OTA is connected to an output terminal of the first-stage OTA. The capacitor module is connected between the output terminal of the first-stage OTA and an output terminal of the second-stage OTA. The clock oscillation circuit is connected to the output terminal of the first-stage OTA and the capacitor module, and is configured to perform charging and discharging of the capacitor module by an output current from the first-stage OTA to output a clock signal. The correction circuit is connected to the clock oscillation circuit and the capacitor module to adjust a capacitance of the capacitor module so that a clock frequency of the clock signal is consistent with a preset clock frequency.

公开(公告)号：US20240195375A1

公开(公告)日：2024-06-13

申请号：US18356519

申请日：2023-07-21

Applicant: Nokia Solutions and Networks Oy

Inventor： Lorenzo Lotti ,  Mark Ferriss ,  Alexander Rylyakov

IPC: H03G3/30 ,  H03F1/30 ,  H03F1/32 ,  H03F3/45 ,  H03G1/00

CPC classification number: H03G3/3084 ,  H03F1/301 ,  H03F1/3211 ,  H03F3/45475 ,  H03G1/0088

Abstract: A transimpedance amplifier (TIA) includes a voltage amplifier and a first set of variable-resistors connected in parallel as a variable shunt feedback to the voltage amplifier. A control circuit is connected to control the variable resistors of the first set in a manner responsive to a TIA gain control voltage VGC. The control circuit includes a ramp generator and a reference set of variable-resistors connected in parallel. The ramp generator is configured to generate, responsive to an output voltage of the control circuit, a plurality of ramp voltages such that each of the voltages adjusts a corresponding one of the variable-resistors of the first set and of the reference set.

公开(公告)号：US11855598B2

公开(公告)日：2023-12-26

申请号：US17895771

申请日：2022-08-25

Applicant: Marvell Asia Pte Ltd.

Inventor： Praveen Prabha ,  Karthik Raviprakash ,  Luke Wang ,  Stephane Dallaire

IPC: H03G3/30 ,  H03F3/45 ,  H03G1/00 ,  H03G3/00

CPC classification number: H03G3/3036 ,  H03G1/0088 ,  H03G3/001 ,  H03F3/45183 ,  H03G2201/502

Abstract: A variable gain amplifier includes input terminals configured to receive a differential input of the variable gain amplifier, output terminals configured to generate a differential output of the variable gain amplifier, the differential output having a gain applied by the variable gain amplifier to the differential input, and an impedance ladder circuit coupled to the input terminals, the impedance ladder circuit comprising a plurality of semiconductor switches configured to receive respective control signals based on a control voltage. The plurality of semiconductors switches are responsive to the respective control signals to adjust the gain of the variable gain amplifier and configured with a predetermined exponential scale such that the impedance ladder circuit causes a slope of the gain of the variable gain amplifier relative to the control voltage to be generally linear.

公开(公告)号：US20230393647A1

公开(公告)日：2023-12-07

申请号：US18446054

申请日：2023-08-08

Applicant: Sonos, Inc.

Inventor： Steve F. Holmgren ,  John L. MacFarlane

IPC: G06F1/3296 ,  H03F99/00 ,  H03F1/52 ,  H04R27/00 ,  G06F3/16 ,  H03F3/183 ,  H03G1/00 ,  H04L69/22 ,  G06F1/3209 ,  G06F1/3246

CPC classification number: G06F1/3296 ,  H04R2227/003 ,  H03F1/52 ,  H04R27/00 ,  G06F3/162 ,  H03F3/183 ,  H03G1/0088 ,  G06F3/165 ,  H04L69/22 ,  G06F1/3209 ,  G06F1/3246 ,  H04R2227/005 ,  H03F2200/03 ,  H04R2420/01 ,  H03F99/00

Abstract: Techniques for controlling one or more audio amplifiers in or associated with a device coupled on a local area network are disclosed. An example playback device includes a processor, an amplifier, a network interface, and a memory. The memory includes a software module that, when executed by the processor, causes the playback device to: operate in a first power mode in which the amplifier consumes a first amount of power; while operating in the first power mode, determine that a defined time has passed since receiving, via the network interface, a specified type of data packet; and based on determining that the defined time has passed since receiving the specified type of data packet, transition from operating in the first power mode to operate in a second power mode in which the amplifier consumes a second amount of power, wherein the first amount of power is greater than the second amount of power.

公开(公告)号：US20230308070A1

公开(公告)日：2023-09-28

申请号：US18069401

申请日：2022-12-21

Applicant: ANRITSU CORPORATION

Inventor： Hirofumi ONO ,  Koji YAMASHITA ,  Shinichi ITO

IPC: H03H7/25 ,  H03G1/00

CPC classification number: H03H7/25 ,  H03G1/0088

Abstract: A signal generation unit 2, a DA converter 3, variable attenuators 40, 42, 44, and 46, a measurement unit 6 that detects a level of the signal attenuated by the variable attenuators 40, 42, 44, and 46 and passed through one or more semiconductor components, a switch 48 that switches between an Internal path through which the signal attenuated by the variable attenuator 40, 42, 44, and 46 is transmitted to the measurement unit 6 and an External path through which the signal attenuated by the variable attenuator 40, 42, 44, and 46 is output from an output terminal 10, and a control unit 7 that obtains a correction value of an attenuation amount of the variable attenuators 40, 42, and 44 with the Internal path and obtains a correction value of an attenuation amount of the variable attenuator 46 with the External path.

公开(公告)号：US11750162B1

公开(公告)日：2023-09-05

申请号：US17887806

申请日：2022-08-15

Applicant: Marvell Asia Pte Ltd.

Inventor： Sagar Ray ,  Jeffrey Wang ,  Karthik Raviprakash

IPC: H03F3/45 ,  H03G1/00 ,  H03F3/72

CPC classification number: H03G1/0088 ,  H03F3/72 ,  H03G1/0029 ,  H03G1/0082 ,  H03F2200/294 ,  H03G1/0023

Abstract: A variable gain amplifier system includes a variable gain amplifier circuit configured to receive an input signal, apply a gain to the input signal, and generate an output signal in accordance with the gain applied to the input signal. The variable gain amplifier circuit is further configured to receive a gain control signal and a bandwidth control signal. A control module is configured to generate the gain control signal to adjust the gain of the variable gain amplifier circuit and generate, separately from the gain control signal, the bandwidth control signal to adjust a bandwidth of the variable gain amplifier circuit by selectively varying an amount of inductance contributed by an inductor circuit of the variable gain amplifier circuit.

公开(公告)号：US20230238931A1

公开(公告)日：2023-07-27

申请号：US17585655

申请日：2022-01-27

Applicant: KING FAHD UNIVERSITY OF PETROLEUM AND MINERALS

Inventor： Salim IBRIR

IPC: H03G3/00 ,  H03G3/30 ,  H03F3/45 ,  H03G1/00

CPC classification number: H03G3/004 ,  H03G3/30 ,  H03F3/45475 ,  H03G1/0088

Abstract: Disclosed are systems and methods for a variable-gain differentiator in series with at least two non-inverting amplifiers. The variable-gain differentiator is connected to a voltage-controlled source at its non-inverting input and to its output at its inverting input. The output is connected to the non-inverting input of the first non-inverting amplifier. The output of the first non-inverting amplifier is connected to the input of the second non-inverting amplifier. The output of the second non-inverting amplifier is connected to a series of three integrators. Each integrator is connected to its output by a feedback path. Varying the gain of the voltage-controlled amplifier varies the gain of the differentiator at the output of the third integrator, thereby varying the output of the system.

公开(公告)号：US20190204360A1

公开(公告)日：2019-07-04

申请号：US16330485

申请日：2017-09-05

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

Inventor： Hassen Hamrita ,  Jean-Michel Bourbotte ,  Vladimir Kondrasovs ,  Hamid Makil

IPC: G01R15/08 ,  G01R15/00 ,  H03G1/00 ,  H03F3/68

CPC classification number: G01R15/08 ,  G01R15/002 ,  G01R19/0023 ,  G01R19/0061 ,  H03F3/68 ,  H03F3/72 ,  H03F2200/393 ,  H03F2200/417 ,  H03F2200/462 ,  H03F2200/78 ,  H03F2203/7236 ,  H03F2203/7239 ,  H03G1/0088 ,  H03G2201/506

Abstract: An amplification device including: a switch including an output that is suitable for being connected to a first or a second input; a first branch that is connected to the first input, which applies a first gain to generate a first amplified signal; a second branch that is connected to the second input, which applies a second gain to generate a second amplified signal; a controller for controlling the switching of the switch to apply the first or the second amplified signal to the output, depending on whether or not the value of a predetermined quantity of the first amplified signal falls within a predetermined range. The first gain and the second gain being non-zero real numbers of opposite sign.

公开(公告)号：US20190181805A1

公开(公告)日：2019-06-13

申请号：US16274016

申请日：2019-02-12

Applicant: NXP USA, Inc.

Inventor： Abdulrhman M. S. Ahmed ,  Mario M. Bokatius ,  Paul R. Hart ,  Joseph Staudinger ,  Richard E, Sweeney

IPC: H03F1/02 ,  H04L7/00 ,  H03F3/21 ,  H03F3/60 ,  H03F3/68 ,  H03F3/189 ,  G06G7/10 ,  H03G1/00 ,  H04L27/22 ,  G06F13/42 ,  H03F3/19

CPC classification number: H03F1/0288 ,  G06F13/4282 ,  G06G7/10 ,  H03F3/189 ,  H03F3/19 ,  H03F3/211 ,  H03F3/602 ,  H03F3/68 ,  H03F2200/387 ,  H03F2200/438 ,  H03F2200/451 ,  H03F2203/21106 ,  H03F2203/21193 ,  H03G1/0088 ,  H03G2201/106 ,  H04L7/0079 ,  H04L27/22

Abstract: Embodiments of circuits for use with an amplifier that includes multiple amplifier paths include a first circuit and a second circuit in parallel with the first circuit. The first circuit includes a first input coupled to a first power divider output, a first output coupled to a first amplifier path of the multiple amplifier paths, and a first adjustable phase shifter and a first attenuator series coupled between the first input and the first output. The second circuit includes a second input coupled to a second power divider output, a second output coupled to a second amplifier path of the multiple amplifier paths, and a second adjustable phase shifter coupled between the second input and the second output.

公开(公告)号：US20190109571A1

公开(公告)日：2019-04-11

申请号：US16152505

申请日：2018-10-05

Applicant: THINE ELECTRONICS, INC.

Inventor： Yuji GENDAI

IPC: H03G1/00 ,  H03F3/45

CPC classification number: H03G1/0088 ,  H03F3/45273 ,  H03F3/45475 ,  H03F2203/45526 ,  H03F2203/45528 ,  H03G1/0029 ,  H03G1/007 ,  H03G3/001

Abstract: A combined resistance circuit 2A includes a first circuitry 20A provided between a first end 2a and a second end 2b. This first circuitry 20A includes a resistor R1 provided between a node N11 and a node N12, a resistor R2 provided between the node N12 and a node N13, a resistor R3 provided between the node N13 and a node N14, a resistor R4 provided between the node N14 and the node N11, a resistor R5 provided between the node N11 and the node N13, a switch SW0 provided in series to the resistor R4 between the node N14 and the node N11, and a switch SW1 provided in series to the resistor R2 between the node N12 and the node N13. The node N12 is connected to the first end and the node N14 is connected to the second end.