公开(公告)号：US20240143513A1

公开(公告)日：2024-05-02

申请号：US17958337

申请日：2022-10-01

Applicant: Intel Corporation

Inventor： Gilbert NEIGER ,  Andreas KLEEN ,  David SHEFFIELD ,  Jason BRANDT ,  Ittai ANATI ,  Vedvyas SHANBHOGUE ,  Ido OUZIEL ,  Michael S. BAIR ,  Barry E. HUNTLEY ,  Joseph NUZMAN ,  Toby OPFERMAN ,  Michael A. ROTHMAN

IPC: G06F12/1009 ,  G06F12/0811 ,  G06F12/1027

CPC classification number: G06F12/1009 ,  G06F12/0811 ,  G06F12/1027

Abstract: An apparatus and method for switching between different types of paging using separate control registers and without disabling paging. For example, one embodiment of a processor comprises: a first control register to store a first base address of a first paging structure associated with a first type of paging having a first number of paging structure levels; a second control register to store a second base address of a second paging structure associated with a first type of paging having a second number of paging structure levels greater than the first number of paging structure levels; page walk circuitry to select either the first base address from the first control register or the second base address from the second control register responsive to a first address translation request, the selection based on a characteristic of program code initiating the address translation request.

公开(公告)号：US20220091995A1

公开(公告)日：2022-03-24

申请号：US17498264

申请日：2021-10-11

Applicant: Intel Corporation

Inventor： Scott Dion RODGERS ,  Robert S. CHAPPELL ,  Barry E. HUNTLEY

IPC: G06F12/1009 ,  G06F12/1027 ,  G06F12/14

Abstract: An apparatus and method for managing different page tables for different privilege levels. For example, one embodiment of a processor comprises: a first control register to store a first base address associated with program code executed at a first privilege level; a second control register to store a second base address associated with program code executed at a second privilege level lower than the first privilege level; and address translation circuitry to identify a first base translation table using the first base address responsive to a first address translation request originating from the program code executed at the first privilege level and to identify a second base translation table using the second base address responsive to a second address translation request originating from the program code executed at the second privilege level.

公开(公告)号：US20200004953A1

公开(公告)日：2020-01-02

申请号：US16024547

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Michael LEMAY ,  David M. DURHAM ,  Michael E. KOUNAVIS ,  Barry E. HUNTLEY ,  Vedvyas SHANBHOGUE ,  Jason W. BRANDT ,  Josh TRIPLETT ,  Gilbert NEIGER ,  Karanvir GREWAL ,  Baiju V. PATEL ,  Ye ZHUANG ,  Jr-Shian TSAI ,  Vadim SUKHOMLINOV ,  Ravi SAHITA ,  Mingwei ZHANG ,  James C. FARWELL ,  Amitabh DAS ,  Krishna BHUYAN

IPC: G06F21/53 ,  G06F12/02

Abstract: Disclosed embodiments relate to encoded inline capabilities. In one example, a system includes a trusted execution environment (TEE) to partition an address space within a memory into a plurality of compartments each associated with code to execute a function, the TEE further to assign a message object in a heap to each compartment, receive a request from a first compartment to send a message block to a specified destination compartment, respond to the request by authenticating the request, generating a corresponding encoded capability, conveying the encoded capability to the destination compartment, and scheduling the destination compartment to respond to the request, and subsequently, respond to a check capability request from the destination compartment by checking the encoded capability and, when the check passes, providing a memory address to access the message block, and, otherwise, generating a fault, wherein each compartment is isolated from other compartments.

公开(公告)号：US20190042467A1

公开(公告)日：2019-02-07

申请号：US16023537

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Ravi SAHITA ,  Barry E. HUNTLEY ,  Vedvyas SHANBHOGUE ,  Dror CASPI ,  Baruch CHAIKIN ,  Gilbert NEIGER ,  Arie AHARON ,  Arumugam THIYAGARAJAH

IPC: G06F12/1036 ,  G06F12/1009 ,  G06F12/14 ,  G06F12/02 ,  G06F9/455

Abstract: Examples include a processor including at least one untrusted extended page table (EPT), circuitry to execute a set of instructions of the instruction set architecture (ISA) of the processor to manage at least one secure extended page table (SEPT), and a physical address translation component to translate a guest physical address of a guest physical memory to a host physical address of a host physical memory using one of the at least one untrusted EPT and the at least one SEPT.