公开(公告)号：US20220206842A1

公开(公告)日：2022-06-30

申请号：US17134339

申请日：2020-12-26

Applicant: INTEL CORPORATION

Inventor： Ravi SAHITA ,  Dror CASPI ,  Vincent SCARLATA ,  Sharon YANIV ,  Baruch CHAIKIN ,  Vedvyas SHANBHOGUE ,  Jun NAKAJIMA ,  Arumugam THIYAGARAJAH ,  Sean CHRISTOPHERSON ,  Haidong XIA ,  Vinay AWASTHI ,  Isaku YAMAHATA ,  Wei WANG ,  Thomas ADELMEYER

IPC: G06F9/48 ,  G06F9/455 ,  G06F9/38 ,  G06F21/60

Abstract: Techniques for migration of a source protected virtual machine from a source platform to a destination platform are descried. A method of an aspect includes enforcing that bundles of state, of a first protected virtual machine (VM), received at a second platform over a stream, during an in-order phase of a migration of the first protected VM from a first platform to the second platform, are imported to a second protected VM of the second platform, in a same order that they were exported from the first protected VM. Receiving a marker over the stream marking an end of the in-order phase. Determining that all bundles of state exported from the first protected VM prior to export of the marker have been imported to the second protected VM. Starting an out-of-order phase of the migration based on the determination that said all bundles of the state exported have been imported.

公开(公告)号：US20240248722A1

公开(公告)日：2024-07-25

申请号：US18626629

申请日：2024-04-04

Applicant: Intel Corporation

Inventor： Eliezer WEISSMANN ,  Mark CHARNEY ,  Michael MISHAELI ,  Robert VALENTINE ,  Itai RAVID ,  Jason W. BRANDT ,  Gilbert NEIGER ,  Baruch CHAIKIN ,  Efraim ROTEM

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3851 ,  G06F9/30043 ,  G06F9/30076 ,  G06F9/30101 ,  G06F9/3836 ,  G06F9/3842

Abstract: Systems, methods, and apparatuses relating to instructions to reset software thread runtime property histories in a hardware processor are described. In one embodiment, a hardware processor includes a hardware guide scheduler comprising a plurality of software thread runtime property histories; a decoder to decode a single instruction into a decoded single instruction, the single instruction having a field that identifies a model-specific register; and an execution circuit to execute the decoded single instruction to check that an enable bit of the model-specific register is set, and when the enable bit is set, to reset the plurality of software thread runtime property histories of the hardware guide scheduler.

公开(公告)号：US20210399882A1

公开(公告)日：2021-12-23

申请号：US17465311

申请日：2021-09-02

Applicant: Intel Corporation

Inventor： Ido OUZIEL ,  Arie AHARON ,  Dror CASPI ,  Baruch CHAIKIN ,  Jacob DOWECK ,  Gideon GERZON ,  Barry E. HUNTLEY ,  Francis X. MCKEEN ,  Gilbert NEIGER ,  Carlos V. ROZAS ,  Ravi L. SAHITA ,  Vedvyas SHANBHOGUE ,  Assaf ZALTSMAN

IPC: H04L9/08 ,  G06F9/455 ,  G06F12/1009 ,  G06F21/60 ,  G06F21/62

Abstract: A processor includes a processor core. A register of the core is to store: a bit range for a number of address bits of physical memory addresses used for key identifiers (IDs), and a first key ID to identify a boundary between non-restricted key IDs and restricted key IDs of the key identifiers. A memory controller is to: determine, via access to bit range and the first key ID in the register, a key ID range of the restricted key IDs within the physical memory addresses; access a processor state that a first logical processor of the processor core executes in an untrusted domain mode; receive a memory transaction, from the first logical processor, including an address associated with a second key ID; and generate a fault in response to a determination that the second key ID is within a key ID range of the restricted key IDs.

公开(公告)号：US20230273795A1

公开(公告)日：2023-08-31

申请号：US18311810

申请日：2023-05-03

Applicant: Intel Corporation

Inventor： Eliezer WEISSMANN ,  Mark CHARNEY ,  Michael MISHAELI ,  Robert VALENTINE ,  Itai RAVID ,  Jason W. BRANDT ,  Gilbert NEIGER ,  Baruch CHAIKIN ,  Efraim ROTEM

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3851 ,  G06F9/30076 ,  G06F9/30101 ,  G06F9/3836

Abstract: Systems, methods, and apparatuses relating to instructions to reset software thread runtime property histories in a hardware processor are described. In one embodiment, a hardware processor includes a hardware guide scheduler comprising a plurality of software thread runtime property histories; a decoder to decode a single instruction into a decoded single instruction, the single instruction having a field that identifies a model-specific register; and an execution circuit to execute the decoded single instruction to check that an enable bit of the model-specific register is set, and when the enable bit is set, to reset the plurality of software thread runtime property histories of the hardware guide scheduler.

公开(公告)号：US20190042467A1

公开(公告)日：2019-02-07

申请号：US16023537

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Ravi SAHITA ,  Barry E. HUNTLEY ,  Vedvyas SHANBHOGUE ,  Dror CASPI ,  Baruch CHAIKIN ,  Gilbert NEIGER ,  Arie AHARON ,  Arumugam THIYAGARAJAH

IPC: G06F12/1036 ,  G06F12/1009 ,  G06F12/14 ,  G06F12/02 ,  G06F9/455

Abstract: Examples include a processor including at least one untrusted extended page table (EPT), circuitry to execute a set of instructions of the instruction set architecture (ISA) of the processor to manage at least one secure extended page table (SEPT), and a physical address translation component to translate a guest physical address of a guest physical memory to a host physical address of a host physical memory using one of the at least one untrusted EPT and the at least one SEPT.