公开(公告)号：US11763183B2

公开(公告)日：2023-09-19

申请号：US17390528

申请日：2021-07-30

Applicant: Intel Corporation

Inventor： Ajit Singh ,  Bharat Daga ,  Michael Behar

IPC: G06N3/08 ,  G06F13/10 ,  G06N3/04 ,  G06N5/046 ,  G06T15/20 ,  G06F17/16 ,  G06F13/28 ,  G06N20/00 ,  G06T9/00

CPC classification number: G06N5/046 ,  G06F13/10 ,  G06F13/28 ,  G06F17/16 ,  G06N3/04 ,  G06N3/08 ,  G06N20/00 ,  G06T9/002 ,  G06T15/205

Abstract: Embodiments described herein provide a processing apparatus comprising compute circuitry to generate neural network data for a convolutional neural network (CNN) and write the neural network data to a memory buffer. The compute circuitry additionally includes a direct memory access (DMA) controller including a hardware codec having encode circuitry and a decode circuitry. The DMA controller reads the neural network data from the memory buffer, encode the neural network data via the encode circuit, writes encoded neural network data to a memory device coupled with the processing apparatus, writes metadata for the encoded neural network data to the memory device coupled with the processing apparatus, and decodes encoded neural network data via the decode circuit in response to a request from the compute circuitry.

公开(公告)号：US11640537B2

公开(公告)日：2023-05-02

申请号：US16378107

申请日：2019-04-08

Applicant: Intel Corporation

Inventor： Bharat Daga ,  Krishnakumar Nair ,  Pradeep Janedula ,  Aravind Babu Srinivasan ,  Bijoy Pazhanimala ,  Ambili Vengallur

IPC: G06N3/10

Abstract: An apparatus to facilitate execution of non-linear functions operations is disclosed. The apparatus comprises accelerator circuitry including a compute grid having a plurality of processing elements to execute neural network computations, store values resulting from the neural network computations, and perform piecewise linear (PWL) approximations of one or more non-linear functions using the stored values as input data.

公开(公告)号：US20210357793A1

公开(公告)日：2021-11-18

申请号：US17390528

申请日：2021-07-30

Applicant: Intel Corporation

Inventor： Ajit Singh ,  Bharat Daga ,  Michael Behar

IPC: G06N5/04 ,  G06T15/20 ,  G06F17/16 ,  G06F13/28 ,  G06N20/00 ,  G06N3/08 ,  G06F13/10 ,  G06T9/00

Abstract: Embodiments described herein provide a processing apparatus comprising compute circuitry to generate neural network data for a convolutional neural network (CNN) and write the neural network data to a memory buffer. The compute circuitry additionally includes a direct memory access (DMA) controller including a hardware codec having encode circuitry and a decode circuitry. The DMA controller reads the neural network data from the memory buffer, encode the neural network data via the encode circuit, writes encoded neural network data to a memory device coupled with the processing apparatus, writes metadata for the encoded neural network data to the memory device coupled with the processing apparatus, and decodes encoded neural network data via the decode circuit in response to a request from the compute circuitry.

公开(公告)号：US11080611B2

公开(公告)日：2021-08-03

申请号：US15853457

申请日：2017-12-22

Applicant: Intel Corporation

Inventor： Ajit Singh ,  Bharat Daga ,  Michael Behar

IPC: G06N3/08 ,  G06F13/10 ,  G06T9/00 ,  G06N5/04 ,  G06T15/20 ,  G06F17/16 ,  G06F13/28 ,  G06N20/00

Abstract: Embodiments described herein provide a processing apparatus comprising compute logic to generate neural network data for a convolutional neural network (CNN) and write the neural network data to a memory buffer. The compute logic additionally includes a direct memory access (DMA) controller including a hardware codec having an encode unit and a decode unit, the DMA controller to read the neural network data from the memory buffer, encode the neural network data via the encode unit, write encoded neural network data to a memory device coupled with the processing apparatus, write metadata for the encoded neural network data to the memory device coupled with the processing apparatus, and decode encoded neural network data via the decode unit in response to a request from the compute logic.

公开(公告)号：US10990648B2

公开(公告)日：2021-04-27

申请号：US15670359

申请日：2017-08-07

Applicant: Intel Corporation

Inventor： Pradeep Janedula ,  Bijoy Pazhanimala ,  Bharat Daga ,  Saurabh Dhoble

IPC: G06F17/15 ,  G06F17/16

Abstract: One embodiment provides a compute apparatus to perform machine learning operations, the compute apparatus comprising a hardware accelerator including a compute unit to perform a Winograd convolution, the compute unit configurable to perform the Winograd convolution for a first kernel size using a transform associated with a second kernel size.