公开(公告)号：US11544191B2

公开(公告)日：2023-01-03

申请号：US16830457

申请日：2020-03-26

Applicant: Intel Corporation

Inventor： Ambili Vengallur ,  Bharat Daga ,  Pradeep K. Janedula ,  Bijoy Pazhanimala ,  Aravind Babu Srinivasan

IPC: G06F12/0811 ,  G06N3/08 ,  G06F7/544

Abstract: Hardware accelerators for accelerated grouped convolution operations. A first buffer of a hardware accelerator may receive a first row of an input feature map (IFM) from a memory. A first group comprising a plurality of tiles may receive a first row of the IFM. A plurality of processing elements of the first group may compute a portion of a first row of an output feature map (OFM) based on the first row of the IFM and a kernel. A second buffer of the accelerator may receive a third row of the IFM from the memory. A second group comprising a plurality of tiles may receive the third row of the IFM. A plurality of processing elements of the second group may compute a portion of a third row of the OFM based on the third row of the IFM and the kernel as part of a grouped convolution operation.

公开(公告)号：US20200320403A1

公开(公告)日：2020-10-08

申请号：US16378107

申请日：2019-04-08

Applicant: Intel Corporation

Inventor： Bharat Daga ,  Krishnakumar Nair ,  Pradeep Janedula ,  Aravind Babu Srinivasan ,  Bijoy Pazhanimala ,  Ambili Vengallur

IPC: G06N3/10

Abstract: An apparatus to facilitate execution of non-linear functions operations is disclosed. The apparatus comprises accelerator circuitry including a compute grid having a plurality of processing elements to execute neural network computations, store values resulting from the neural network computations, and perform piecewise linear (PWL) approximations of one or more non-linear functions using the stored values as input data.

公开(公告)号：US11640537B2

公开(公告)日：2023-05-02

申请号：US16378107

申请日：2019-04-08

Applicant: Intel Corporation

Inventor： Bharat Daga ,  Krishnakumar Nair ,  Pradeep Janedula ,  Aravind Babu Srinivasan ,  Bijoy Pazhanimala ,  Ambili Vengallur

IPC: G06N3/10

Abstract: An apparatus to facilitate execution of non-linear functions operations is disclosed. The apparatus comprises accelerator circuitry including a compute grid having a plurality of processing elements to execute neural network computations, store values resulting from the neural network computations, and perform piecewise linear (PWL) approximations of one or more non-linear functions using the stored values as input data.

公开(公告)号：US10990648B2

公开(公告)日：2021-04-27

申请号：US15670359

申请日：2017-08-07

Applicant: Intel Corporation

Inventor： Pradeep Janedula ,  Bijoy Pazhanimala ,  Bharat Daga ,  Saurabh Dhoble

IPC: G06F17/15 ,  G06F17/16

Abstract: One embodiment provides a compute apparatus to perform machine learning operations, the compute apparatus comprising a hardware accelerator including a compute unit to perform a Winograd convolution, the compute unit configurable to perform the Winograd convolution for a first kernel size using a transform associated with a second kernel size.