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11.
公开(公告)号:US20210049804A1
公开(公告)日:2021-02-18
申请号:US17006253
申请日:2020-08-28
Applicant: Intel Corporation
Inventor: Uzi Sarel , Ehud Cohen , Tomer Schwartz , Amitai Armon , Yahav Shadmiy , Itamar Ben-Ari , Amit Bleiweiss , Lev Faivishevsky , Tomer Bar-On , Yaniv Fais , Jacob Subag , Michael Behar , Guy Jacob , Gal Leibovich , Jeremie Dreyfuss
Abstract: In an example, an apparatus comprises a plurality of execution units; and logic, at least partially including hardware logic, to determine a sub-graph of a network that can be executed in a frequency domain and apply computations in the sub-graph in the frequency domain. Other embodiments are also disclosed and claimed.
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公开(公告)号:US10853035B2
公开(公告)日:2020-12-01
申请号:US16833128
申请日:2020-03-27
Applicant: Intel Corporation
Inventor: Yaniv Fais , Tomer Bar-On , Jacob Subag , Jeremie Dreyfuss , Lev Faivishevsky , Michael Behar , Amit Bleiweiss , Guy Jacob , Gal Leibovich , Itamar Ben-Ari , Galina Ryvchin , Eyal Yaacoby
Abstract: In an example, an apparatus comprises a plurality of execution units and logic, at least partially including hardware logic, to gate at least one of a multiply unit or an accumulate unit in response to an input of value zero. Other embodiments are also disclosed and claimed.
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公开(公告)号:US10372416B2
公开(公告)日:2019-08-06
申请号:US15499893
申请日:2017-04-28
Applicant: Intel Corporation
Inventor: Yaniv Fais , Tomer Bar-On , Jacob Subag , Jeremie Dreyfuss , Lev Faivishevsky , Michael Behar , Amit Bleiweiss , Guy Jacob , Gal Leibovich , Itamar Ben-Ari , Galina Ryvchin , Eyal Yaacoby
Abstract: In an example, an apparatus comprises a plurality of execution units and logic, at least partially including hardware logic, to gate at least one of a multiply unit or an accumulate unit in response to an input of value zero. Other embodiments are also disclosed and claimed.
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公开(公告)号:US20180314934A1
公开(公告)日:2018-11-01
申请号:US15499900
申请日:2017-04-28
Applicant: Intel Corporation
Inventor: Eran Ben-Avi , Neta Zmora , Guy Jacob , Lev Faivishevsky , Jeremie Dreyfuss , Tomer Bar-On , Jacob Subag , Yaniv Fais , Shira Hirsh , Orly Weisel , Zigi Walter , Yarden Oren
Abstract: In an example, an apparatus comprises a plurality of execution units comprising and logic, at least partially including hardware logic, to traverse a solution space, score a plurality of solutions to a scheduling deep learning network execution, and select a preferred solution from the plurality of solutions to implement the deep learning network. Other embodiments are also disclosed and claimed.
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公开(公告)号:US20150193507A1
公开(公告)日:2015-07-09
申请号:US14127951
申请日:2013-08-06
Applicant: INTEL CORPORATION
Inventor: Rinat Rappoport , Raanan Yehezkel , Roman Fishtein , Sergei Goffman , Guy Jacob , Oren Gershon , Andrey Sloutsman , Ido Lapidot , Ofer Givoli
CPC classification number: G06F17/30528 , G06K9/00302 , G06Q10/101 , G06T2207/30201
Abstract: Embodiments of techniques, apparatuses and systems associated with emotion information processing are disclosed. In some embodiments, a computing system may receive an image of a person and identify an emotional state of the person, based at least in part on the image. The computing system may cause storage of the emotional state of the person in combination with other data to enable subsequent response to an emotion-related query provided to the computing system. The emotion-related query may include an emotion-related criteria and a non-emotion-related criteria and the response may be based at least in part on the emotional state in combination with at least some of the other data. Other embodiments may be described and/or claimed.
Abstract translation: 公开了与情绪信息处理相关联的技术,装置和系统的实施例。 在一些实施例中,计算系统可以至少部分地基于图像来接收人的图像并且识别人的情绪状态。 计算系统可以使人的情绪状态与其他数据结合存储,以便能够随后响应提供给计算系统的情感相关查询。 情感相关查询可以包括情感相关标准和非情感相关标准,并且响应可以至少部分地基于情绪状态与至少一些其他数据的组合。 可以描述和/或要求保护其他实施例。
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公开(公告)号:US12033063B2
公开(公告)日:2024-07-09
申请号:US18174275
申请日:2023-02-24
Applicant: Intel Corporation
Inventor: Eran Ben-Avi , Neta Zmora , Guy Jacob , Lev Faivishevsky , Jeremie Dreyfuss , Tomer Bar-On , Jacob Subag , Yaniv Fais , Shira Hirsch , Orly Weisel , Zigi Walter , Yarden Oren
Abstract: In an example, an apparatus comprises a plurality of execution units comprising and logic, at least partially including hardware logic, to traverse a solution space, score a plurality of solutions to a scheduling deep learning network execution, and select a preferred solution from the plurality of solutions to implement the deep learning network. Other embodiments are also disclosed and claimed.
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公开(公告)号:US20230281435A1
公开(公告)日:2023-09-07
申请号:US18174275
申请日:2023-02-24
Applicant: Intel Corporation
Inventor: Eran Ben-Avi , Neta Zmora , Guy Jacob , Lev Faivishevsky , Jeremie Dreyfuss , Tomer Bar-On , Jacob Subag , Yaniv Fais , Shira Hirsch , Orly Weisel , Zigi Walter , Yarden Oren
Abstract: In an example, an apparatus comprises a plurality of execution units comprising and logic, at least partially including hardware logic, to traverse a solution space, score a plurality of solutions to a scheduling deep learning network execution, and select a preferred solution from the plurality of solutions to implement the deep learning network. Other embodiments are also disclosed and claimed.
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公开(公告)号:US11599777B2
公开(公告)日:2023-03-07
申请号:US15499900
申请日:2017-04-28
Applicant: Intel Corporation
Inventor: Eran Ben-Avi , Neta Zmora , Guy Jacob , Lev Faivishevsky , Jeremie Dreyfuss , Tomer Bar-On , Jacob Subag , Yaniv Fais , Shira Hirsch , Orly Weisel , Zigi Walter , Yarden Oren
Abstract: In an example, an apparatus comprises a plurality of execution units comprising and logic, at least partially including hardware logic, to traverse a solution space, score a plurality of solutions to a scheduling deep learning network execution, and select a preferred solution from the plurality of solutions to implement the deep learning network. Other embodiments are also disclosed and claimed.
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19.
公开(公告)号:US11250610B2
公开(公告)日:2022-02-15
申请号:US17006253
申请日:2020-08-28
Applicant: Intel Corporation
Inventor: Uzi Sarel , Ehud Cohen , Tomer Schwartz , Amitai Armon , Yahav Shadmiy , Itamar Ben-Ari , Amit Bleiweiss , Lev Faivishevsky , Tomer Bar-On , Yaniv Fais , Jacob Subag , Michael Behar , Guy Jacob , Gal Leibovich , Jeremie Dreyfuss
Abstract: In an example, an apparatus comprises a plurality of execution units; and logic, at least partially including hardware logic, to determine a sub-graph of a network that can be executed in a frequency domain and apply computations in the sub-graph in the frequency domain. Other embodiments are also disclosed and claimed.
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公开(公告)号:US20200293282A1
公开(公告)日:2020-09-17
申请号:US16833128
申请日:2020-03-27
Applicant: Intel Corporation
Inventor: YANIV Fais , Tomer Bar-On , Jacob Subag , Jeremie Dreyfuss , Lev Faivishevsky , Michael Behar , Amit Bleiweiss , Guy Jacob , Gal Leibovich , Itamar Ben-Ari , Galina Ryvchin , Eyal Yaacoby
Abstract: In an example, an apparatus comprises a plurality of execution units and logic, at least partially including hardware logic, to gate at least one of a multiply unit or an accumulate unit in response to an input of value zero. Other embodiments are also disclosed and claimed.
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