公开(公告)号：US11704226B2

公开(公告)日：2023-07-18

申请号：US17483431

申请日：2021-09-23

Applicant: Intel Corporation

Inventor： Niranjan Hasabnis ,  Justin Gottschlich ,  Jeremie Dreyfuss ,  Amitai Armon ,  Itamar Ben-Ari ,  Oren David Kimhi

IPC: G06F9/44 ,  G06F11/36 ,  G06F8/40 ,  G06F8/73

CPC classification number: G06F11/3648 ,  G06F8/40 ,  G06F8/73

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed to detect code defects. An example apparatus includes repository interface circuitry to retrieve code repositories corresponding to a programming language of interest, tree generating circuitry to generate parse trees corresponding to code blocks contained in the code repositories, directed acyclic graph (DAG) circuitry to generate DAGs corresponding to respective ones of the parse trees, the DAGs including control flow information and data flow information, abstraction generating circuitry to abstract the DAGs, invariant identification circuitry to extract invariants from the abstracted DAGs, and DAG comparison circuitry to cluster respective ones of the extracted invariants to identify respective ones of the abstracted DAGs with common invariants.

公开(公告)号：US11600035B2

公开(公告)日：2023-03-07

申请号：US17669126

申请日：2022-02-10

Applicant: Intel Corporation

Inventor： Uzi Sarel ,  Ehud Cohen ,  Tomer Schwartz ,  Amitai Armon ,  Yahav Shadmiy ,  Itamar Ben-Ari ,  Amit Bleiweiss ,  Lev Faivishevsky ,  Tomer Bar-On ,  Yaniv Fais ,  Jacob Subag ,  Michael Behar ,  Guy Jacob ,  Gal Leibovich ,  Jeremie Dreyfuss

IPC: G06N3/04 ,  G06N3/08 ,  G06N3/063 ,  G06T15/00 ,  G06N3/02

Abstract: In an example, an apparatus comprises a plurality of execution units; and logic, at least partially including hardware logic, to determine a sub-graph of a network that can be executed in a frequency domain and apply computations in the sub-graph in the frequency domain. Other embodiments are also disclosed and claimed.

公开(公告)号：US10769862B2

公开(公告)日：2020-09-08

申请号：US16053135

申请日：2018-08-02

Applicant: INTEL CORPORATION

Inventor： Amit Bleiweiss ,  Chen Paz ,  Ofir Levy ,  Itamar Ben-Ari ,  Yaron Yanai

IPC: G06T15/00 ,  G06T19/20 ,  G06N20/00 ,  G06K9/00 ,  G06F30/00 ,  G06T3/20 ,  G06T3/40 ,  G06T3/60 ,  G06T15/20 ,  G06T15/50 ,  G06T17/00

Abstract: Techniques are provided for generation of synthetic 3-dimensional object image variations for training of recognition systems. An example system may include an image synthesizing circuit configured to synthesize a 3D image of the object (including color and depth image pairs) based on a 3D model. The system may also include a background scene generator circuit configured to generate a background for each of the rendered image variations. The system may further include an image pose adjustment circuit configured to adjust the orientation and translation of the object for each of the variations. The system may further include an illumination and visual effect adjustment circuit configured to adjust illumination of the object and the background for each of the variations, and to further adjust visual effects of the object and the background for each of the variations based on application of simulated camera parameters.

公开(公告)号：US10762685B2

公开(公告)日：2020-09-01

申请号：US16670749

申请日：2019-10-31

Applicant: Intel Corporation

Inventor： Uzi Sarel ,  Ehud Cohen ,  Tomer Schwartz ,  Amitai Armon ,  Yahav Shadmiy ,  Itamar Ben-Ari ,  Amit Bleiweiss ,  Lev Faivishevsky ,  Tomer Bar-On ,  Yaniv Fais ,  Jacob Subag ,  Michael Behar ,  Guy Jacob ,  Gal Leibovich ,  Jeremie Dreyfuss

IPC: G06N3/02 ,  G06N3/08 ,  G06N3/063 ,  G06T15/00 ,  G06N3/04

Abstract: In an example, an apparatus comprises a plurality of execution units; and logic, at least partially including hardware logic, to determine a sub-graph of a network that can be executed in a frequency domain and apply computations in the sub-graph in the frequency domain. Other embodiments are also disclosed and claimed.

公开(公告)号：US20200143579A1

公开(公告)日：2020-05-07

申请号：US16670749

申请日：2019-10-31

Applicant: Intel Corporation

Inventor： Uzi Sarel ,  Ehud Cohen ,  Tomer Schwartz ,  Amitai Armon ,  Yahav Shadmiy ,  Itamar Ben-Ari ,  Amit Bleiweiss ,  Lev Faivishevsky ,  Tomer Bar-On ,  Yaniv Fais ,  Jacob Subag ,  Michael Behar ,  Guy Jacob ,  Gal Leibovich ,  Jeremie Dreyfuss

IPC: G06T15/00 ,  G06N3/02 ,  G06N3/04 ,  G06N3/063 ,  G06N3/08

Abstract: In an example, an apparatus comprises a plurality of execution units; and logic, at least partially including hardware logic, to determine a sub-graph of a network that can be executed in a frequency domain and apply computations in the sub-graph in the frequency domain. Other embodiments are also disclosed and claimed.

公开(公告)号：US20180293777A1

公开(公告)日：2018-10-11

申请号：US15482724

申请日：2017-04-08

Applicant: Intel Corporation

Inventor： Uzi Sarel ,  Ehud Cohen ,  Tomer Schwartz ,  Amitai Armon ,  Yahav Shadmiy ,  Itamar Ben-Ari ,  Amit Bleiweiss ,  Lev Faivishevsky ,  Tomer Bar-On ,  Yaniv Fais ,  Jacob Subag ,  Michael Behar ,  Guy Jacob ,  Gal Leibovich ,  Jeremie Dreyfuss

IPC: G06T15/00 ,  G06N3/04 ,  G06N3/08

Abstract: In an example, an apparatus comprises a plurality of execution units; and logic, at least partially including hardware logic, to determine a sub-graph of a network that can be executed in a frequency domain and apply computations in the sub-graph in the frequency domain. Other embodiments are also disclosed and claimed.

公开(公告)号：US20170169620A1

公开(公告)日：2017-06-15

申请号：US14969563

申请日：2015-12-15

Applicant: INTEL CORPORATION

Inventor： Amit Bleiweiss ,  Chen Paz ,  Ofir Levy ,  Itamar Ben-Ari ,  Yaron Yanai

IPC: G06T19/20 ,  G06T3/40 ,  G06T3/60 ,  G06F17/50 ,  G06T15/50 ,  G06T17/00 ,  G06N99/00 ,  G06T15/20 ,  G06T3/20

CPC classification number: G06T19/20 ,  G06F17/50 ,  G06K9/00201 ,  G06K2209/40 ,  G06N99/005 ,  G06T3/20 ,  G06T3/40 ,  G06T3/60 ,  G06T15/00 ,  G06T15/20 ,  G06T15/50 ,  G06T17/00

Abstract: Techniques are provided for generation of synthetic 3-dimensional object image variations for training of recognition systems. An example system may include an image synthesizing circuit configured to synthesize a 3D image of the object (including color and depth image pairs) based on a 3D model. The system may also include a background scene generator circuit configured to generate a background for each of the rendered image variations. The system may further include an image pose adjustment circuit configured to adjust the orientation and translation of the object for each of the variations. The system may further include an illumination and visual effect adjustment circuit configured to adjust illumination of the object and the background for each of the variations, and to further adjust visual effects of the object and the background for each of the variations based on application of simulated camera parameters.

公开(公告)号：US11250610B2

公开(公告)日：2022-02-15

申请号：US17006253

申请日：2020-08-28

Applicant: Intel Corporation

Inventor： Uzi Sarel ,  Ehud Cohen ,  Tomer Schwartz ,  Amitai Armon ,  Yahav Shadmiy ,  Itamar Ben-Ari ,  Amit Bleiweiss ,  Lev Faivishevsky ,  Tomer Bar-On ,  Yaniv Fais ,  Jacob Subag ,  Michael Behar ,  Guy Jacob ,  Gal Leibovich ,  Jeremie Dreyfuss

IPC: G06N3/04 ,  G06N3/08 ,  G06N3/02 ,  G06T15/00 ,  G06N3/063

Abstract: In an example, an apparatus comprises a plurality of execution units; and logic, at least partially including hardware logic, to determine a sub-graph of a network that can be executed in a frequency domain and apply computations in the sub-graph in the frequency domain. Other embodiments are also disclosed and claimed.

公开(公告)号：US20210056768A1

公开(公告)日：2021-02-25

申请号：US17012881

申请日：2020-09-04

Applicant: INTEL CORPORATION

Inventor： Amit Bleiweiss ,  Chen Paz ,  Ofir Levy ,  Itamar Ben-Ari ,  Yaron Yanai

IPC: G06T19/20 ,  G06N20/00 ,  G06K9/00 ,  G06T15/00 ,  G06F30/00 ,  G06T3/20 ,  G06T3/40 ,  G06T3/60 ,  G06T15/20 ,  G06T15/50 ,  G06T17/00

Abstract: Techniques are provided for generation of synthetic 3-dimensional object image variations for training of recognition systems. An example system may include an image synthesizing circuit configured to synthesize a 3D image of the object (including color and depth image pairs) based on a 3D model. The system may also include a background scene generator circuit configured to generate a background for each of the rendered image variations. The system may further include an image pose adjustment circuit configured to adjust the orientation and translation of the object for each of the variations. The system may further include an illumination and visual effect adjustment circuit configured to adjust illumination of the object and the background for each of the variations, and to further adjust visual effects of the object and the background for each of the variations based on application of simulated camera parameters.

公开(公告)号：US20200293282A1

公开(公告)日：2020-09-17

申请号：US16833128

申请日：2020-03-27

Applicant: Intel Corporation

Inventor： YANIV Fais ,  Tomer Bar-On ,  Jacob Subag ,  Jeremie Dreyfuss ,  Lev Faivishevsky ,  Michael Behar ,  Amit Bleiweiss ,  Guy Jacob ,  Gal Leibovich ,  Itamar Ben-Ari ,  Galina Ryvchin ,  Eyal Yaacoby

IPC: G06F7/533 ,  G06N20/00 ,  G06T1/20

Abstract: In an example, an apparatus comprises a plurality of execution units and logic, at least partially including hardware logic, to gate at least one of a multiply unit or an accumulate unit in response to an input of value zero. Other embodiments are also disclosed and claimed.