公开(公告)号：US20150092863A1

公开(公告)日：2015-04-02

申请号：US14563026

申请日：2014-12-08

Applicant: Intel Corporation

Inventor： Jorge E. Caviedes ,  Mahesh Subedar ,  Khasim S. Kudekula

IPC: H04N19/136 ,  H04N19/80 ,  H04N19/44

CPC classification number: H04N19/80 ,  H04N19/117 ,  H04N19/136 ,  H04N19/14 ,  H04N19/172 ,  H04N19/176 ,  H04N19/182 ,  H04N19/44 ,  H04N19/86 ,  H04W84/18

Abstract: Apparatus, systems and methods for adaptively reducing blocking artifacts in block-coded video are disclosed. In one implementation, a system includes processing logic at least capable of deblock filtering at least a portion of a line of video data based, at least in part, on edge information and texture information to generate at least a portion of a line of deblocked video data, and an image data output device responsive to the processing logic.

Abstract translation: 公开了用于自动减少块编码视频中的块伪影的装置，系统和方法。 在一个实现中，系统包括至少能够至少部分地基于边缘信息和纹理信息来对视频数据行的至少一部分进行去块滤波的处理逻辑，以生成解锁视频行的至少一部分 数据和响应于处理逻辑的图像数据输出装置。

公开(公告)号：US11546639B2

公开(公告)日：2023-01-03

申请号：US17488062

申请日：2021-09-28

Applicant: INTEL CORPORATION

Inventor： Jorge E. Caviedes ,  Mahesh M. Subedar ,  Khasim S. Dudekula

IPC: H04N19/80 ,  H04N19/117 ,  H04N19/86 ,  H04N19/136 ,  H04N19/44 ,  H04N19/176 ,  H04N19/14 ,  H04N19/172 ,  H04N19/182 ,  H04W84/18

Abstract: Apparatus, systems and methods for adaptively reducing blocking artifacts in block-coded video are disclosed. In one implementation, a system includes processing logic at least capable of deblock filtering at least a portion of a line of video data based, at least in part, on edge information and texture information to generate at least a portion of a line of deblocked video data, and an image data output device responsive to the processing logic.

公开(公告)号：US20210014538A1

公开(公告)日：2021-01-14

申请号：US17037279

申请日：2020-09-29

Applicant: INTEL CORPORATION

Inventor： Jorge E. Caviedes ,  Mahesh M. Subedar ,  Khasim S. Dudekula

IPC: H04N19/80 ,  H04N19/117 ,  H04N19/86 ,  H04N19/136 ,  H04N19/44 ,  H04N19/176 ,  H04N19/14

Abstract: Apparatus, systems and methods for adaptively reducing blocking artifacts in block-coded video are disclosed. In one implementation, a system includes processing logic at least capable of deblock filtering at least a portion of a line of video data based, at least in part, on edge information and texture information to generate at least a portion of a line of deblocked video data, and an image data output device responsive to the processing logic.

公开(公告)号：US20200107046A1

公开(公告)日：2020-04-02

申请号：US16593710

申请日：2019-10-04

Applicant: INTEL CORPORATION

Inventor： Jorge E. Caviedes ,  Mahesh M. Subedar ,  Khasim S. Dudekula

IPC: H04N19/80 ,  H04N19/14 ,  H04N19/176 ,  H04N19/44 ,  H04N19/136 ,  H04N19/86 ,  H04N19/117

Abstract: Apparatus, systems and methods for adaptively reducing blocking artifacts in block-coded video are disclosed. In one implementation, a system includes processing logic at least capable of deblock filtering at least a portion of a line of video data based, at least in part, on edge information and texture information to generate at least a portion of a line of deblocked video data, and an image data output device responsive to the processing logic.

公开(公告)号：US10440395B2

公开(公告)日：2019-10-08

申请号：US15271152

申请日：2016-09-20

Applicant: Intel Corporation

Inventor： Jorge E. Caviedes ,  Mahesh M. Subedar ,  Khasim S. Dudekula

IPC: H04N19/86 ,  H04N19/80 ,  H04N19/117 ,  H04N19/136 ,  H04N19/44 ,  H04N19/176 ,  H04N19/14 ,  H04N19/172 ,  H04N19/182 ,  H04W84/18

Abstract: Apparatus, systems and methods for adaptively reducing blocking artifacts in block-coded video are disclosed. In one implementation, a system includes processing logic at least capable of deblock filtering at least a portion of a line of video data based, at least in part, on edge information and texture information to generate at least a portion of a line of deblocked video data, and an image data output device responsive to the processing logic.

公开(公告)号：US20180005387A1

公开(公告)日：2018-01-04

申请号：US15200567

申请日：2016-07-01

Applicant: INTEL CORPORATION

Inventor： Yeongseon Lee ,  Nilesh A. Ahuja ,  Mahesh Subedar ,  Jorge E. Caviedes

IPC: G06T7/269 ,  G06T3/40 ,  H04N1/48 ,  H04N19/182

CPC classification number: G06T7/269 ,  G06T2207/10016 ,  H04N19/102 ,  H04N19/137 ,  H04N19/14 ,  H04N19/17 ,  H04N19/182 ,  H04N19/51

Abstract: Techniques are provided for detection and location of active display regions in videos with static borders. A methodology implementing the techniques according to an embodiment includes extracting features from rows and columns of pixels of a video frame. The features are based on horizontal gradient runs (HGRs) and vertical gradient runs (VGRs). The method also includes detecting one or more static regions of the frame, based on a comparison of differences between the features of the current video frame and features extracted from a previous video frame. The method further includes detecting one or more boundaries of the static regions based on a location of a maximum value of one of the features within the static region, if the maximum value is greater than a boundary detection threshold value. Determination of the active region in the current video frame is based on exclusion of the detected static regions.

公开(公告)号：US09641800B2

公开(公告)日：2017-05-02

申请号：US14725777

申请日：2015-05-29

Applicant: INTEL CORPORATION

Inventor： Jorge E. Caviedes ,  Sin Lin Wu

IPC: H04N7/14 ,  H04N7/15 ,  H04N13/04

CPC classification number: H04N7/15 ,  H04N7/142 ,  H04N7/147 ,  H04N13/25 ,  H04N13/257 ,  H04N13/261 ,  H04N13/349 ,  H04N13/38 ,  H04N13/383 ,  H04N2007/145 ,  H04N2213/006

Abstract: Three-dimensional video is presented on a two-dimensional display. The view of the video is driven by user interaction. In one example, a two-dimensional (2D) video sequence in real time with a first view is synthesized from a video image sequence with depth captured by a first device. The 2D video sequence with the first view is provided to a second device in real time. A command is received from the second device to change a view of the 2D video sequence as the video sequence is rendered. The view of the 2D video sequence is changed as it is rendered to a 2D video sequence with a second view, and the 2D video sequence with the second view is provided to the second device in real time.

公开(公告)号：US11936915B2

公开(公告)日：2024-03-19

申请号：US18090310

申请日：2022-12-28

Applicant: INTEL CORPORATION

Inventor： Jorge E. Caviedes ,  Mahesh M. Subedar ,  Khasim S. Dudekula

IPC: H04N19/80 ,  H04N19/117 ,  H04N19/136 ,  H04N19/14 ,  H04N19/176 ,  H04N19/44 ,  H04N19/86 ,  H04N19/172 ,  H04N19/182 ,  H04W84/18

CPC classification number: H04N19/80 ,  H04N19/117 ,  H04N19/136 ,  H04N19/14 ,  H04N19/176 ,  H04N19/44 ,  H04N19/86 ,  H04N19/172 ,  H04N19/182 ,  H04W84/18

Abstract: Apparatus, systems and methods for adaptively reducing blocking artifacts in block-coded video are disclosed. In one implementation, a system includes processing logic at least capable of deblock filtering at least a portion of a line of video data based, at least in part, on edge information and texture information to generate at least a portion of a line of deblocked video data, and an image data output device responsive to the processing logic.

公开(公告)号：US20220021906A1

公开(公告)日：2022-01-20

申请号：US17488062

申请日：2021-09-28

Applicant: INTEL CORPORATION

Inventor： Jorge E. Caviedes ,  Mahesh M. Subedar ,  Khasim S. Dudekula

IPC: H04N19/80 ,  H04N19/117 ,  H04N19/86 ,  H04N19/136 ,  H04N19/44 ,  H04N19/176 ,  H04N19/14

Abstract: Apparatus, systems and methods for adaptively reducing blocking artifacts in block-coded video are disclosed. In one implementation, a system includes processing logic at least capable of deblock filtering at least a portion of a line of video data based, at least in part, on edge information and texture information to generate at least a portion of a line of deblocked video data, and an image data output device responsive to the processing logic.

公开(公告)号：US09710890B2

公开(公告)日：2017-07-18

申请号：US14704116

申请日：2015-05-05

Applicant: Intel Corporation

Inventor： Abhijit Sarkar ,  Jorge E. Caviedes ,  Mahesh Subedar

IPC: H04N5/57 ,  G06T5/00 ,  H04N1/60

CPC classification number: G06T5/00 ,  G06T5/003 ,  G06T5/007 ,  G06T2207/10016 ,  G06T2207/10024 ,  H04N1/6005 ,  H04N1/6027 ,  H04N1/608

Abstract: In some embodiments, color and contrast enhancement video processing may be done in one shot instead of adjusting one of color and contrast enhancement, then the other, and then going back to the first one to readjust because of the second adjustment. In some embodiments, global lightness adjustment, local contrast enhancement, and saturation enhancement may be done at the same time and in parallel. Lightness adjustment improves visibility of details for generally dark or generally light images without changing intended lighting conditions in the original shot, and is used to enhance the range of color/saturation enhancement. Local contrast enhancement done in parallel improves visual definition of objects and textures and thus local contrast and perceived sharpness.