公开(公告)号：US11182240B2

公开(公告)日：2021-11-23

申请号：US17032567

申请日：2020-09-25

Applicant: Intel Corporation

Inventor： Santhosh K. Vanaparthy ,  Zion S. Kwok ,  Ravi H. Motwani

IPC: G06F11/10 ,  H03M13/21 ,  H03M13/29 ,  H03M13/00 ,  H03M13/11 ,  H03M13/39

Abstract: Examples include techniques to improve error correction using an exclusive OR (XOR) rebuild scheme that includes two uncorrectable codewords. Examples include generation of soft XOR codewords using bits of correctable codewords to rebuild a codeword read from a memory that has uncorrectable errors and adjust bit reliability information to generate a new codeword having correctable errors. Examples also include techniques to prevent mis-correction due to read reference voltage shifts using non-linear transformations.

公开(公告)号：US11159175B2

公开(公告)日：2021-10-26

申请号：US16448935

申请日：2019-06-21

Applicant: Intel Corporation

Inventor： Santhosh K. Vanaparthy ,  Ravi H. Motwani

IPC: H03M13/00 ,  H03M13/11 ,  G11C29/52 ,  G06F11/10

Abstract: Systems, apparatuses and methods may provide for technology to receive a codeword containing an SC-LDPC code and conduct a min-sum decode of the SC-LDPC code based on a plurality of scaling factors. In an embodiment, the scaling factors are non-uniform across check nodes and multiple iterations of the min-sum decode.

公开(公告)号：US20210175901A1

公开(公告)日：2021-06-10

申请号：US17183223

申请日：2021-02-23

Applicant: Intel Corporation

Inventor： Debarnab Mitra ,  Santhosh K. Vanaparthy

IPC: H03M13/11 ,  G06F11/10

Abstract: An embodiment of an electronic apparatus may comprise one or more substrates, and a decoder coupled to the one or more substrates, the decoder including logic to perform a first decode stage with a first fixed quantization width, and perform a second decode stage with a second fixed quantization width that is different from the first fixed quantization width. Other embodiments are disclosed and claimed.

公开(公告)号：US20190312594A1

公开(公告)日：2019-10-10

申请号：US16448935

申请日：2019-06-21

Applicant: Intel Corporation

Inventor： Santhosh K. Vanaparthy ,  Ravi H. Motwani

IPC: H03M13/11 ,  G06F11/10 ,  G11C29/52 ,  H03M13/00

Abstract: Systems, apparatuses and methods may provide for technology to receive a codeword containing an SC-LDPC code and conduct a min-sum decode of the SC-LDPC code based on a plurality of scaling factors. In an embodiment, the scaling factors are non-uniform across check nodes and multiple iterations of the min-sum decode.

公开(公告)号：US20190102248A1

公开(公告)日：2019-04-04

申请号：US15721291

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Santhosh K. Vanaparthy ,  Ravi H. Motwani ,  Zion S. Kwok

IPC: G06F11/10 ,  G11C29/52 ,  H03M13/37

Abstract: One embodiment provides a silent data corruption (SDC) mitigation circuitry. The SDC mitigation circuitry includes a comparator circuitry and an SDC mitigation logic. The comparator circuitry is to compare a successful decoded codeword and a corresponding received codeword, the successful decoded codeword having been deemed a success by an error correction circuitry. The SDC mitigation logic is to reject the successful decoded codeword if a distance between the corresponding received codeword and the successful decoded codeword is greater than or equal to a threshold.