公开(公告)号：US20110093829A1

公开(公告)日：2011-04-21

申请号：US12904409

申请日：2010-10-14

申请人： Takahiko Orita ,  Kazunori Kumagai ,  Yoshitaka Nishio ,  Ikuo Ohtsuka ,  Motoyuki Tanisho

发明人： Takahiko Orita ,  Kazunori Kumagai ,  Yoshitaka Nishio ,  Ikuo Ohtsuka ,  Motoyuki Tanisho

IPC分类号： G06F17/50

CPC分类号： G06F17/5077 ,  H05K3/0005

摘要： A non-transitory, computer-readable recording medium stores therein a design support program that causes a computer to execute selecting a wiring path whose line length is greatest among a plurality of wiring paths making up a wiring group leading from a transmission origin to a transmission destination; detecting insufficient line lengths of the wiring paths not selected, insufficiency being determined with respect to the line length of the selected wiring path; calculating the area of insufficiency according to a sum of the detected insufficient line lengths; allocating to a vicinity of the wiring group, a line length adjustment region corresponding to a sum of the areas of insufficiency calculated at calculating; and controlling a display screen to display the wiring group and the allocated line length adjustment region.

摘要翻译： 一种非暂时的计算机可读记录介质，其中存储有一个设计支持程序，使计算机执行选择构成从传输来源到传输的布线组的多个布线路径中线路长度最大的布线路径 目的地; 检测未选择的布线路径的线路长度不足，相对于所选择的布线路径的线路长度来确定不足; 根据检测到的不足线长度的总和计算不足的面积; 分配给布线组附近的线长度调整区域，与计算时计算出的功能不足区域的和相对应; 并且控制显示屏幕以显示配线组和所分配的线路长度调节区域。

公开(公告)号：US07984413B2

公开(公告)日：2011-07-19

申请号：US12222229

申请日：2008-08-05

申请人： Takahiko Orita ,  Eiichi Konno

发明人： Takahiko Orita ,  Eiichi Konno

IPC分类号： G06F17/50

CPC分类号： G06F17/5077

摘要： A wiring design processing method is for designing an automatic wiring processing process as an execution sequence of various processing in automatic wiring processing for printed circuit boards by using a computer. The wiring design processing method includes storing, in a storage unit, printed circuit board information including various physical information regarding the printed circuit boards, for each of the printed circuit boards; creating an automatic wiring processing process automatically according to a result of analyzing setting, wiring progress, and wiring situation at present regarding each of the printed circuit boards, after reading the printed circuit board information, stored in the storage unit at the storing, for each of the printed circuit boards; and executing the automatic wiring processing according to the automatic wiring processing process created at the creating, for each of the printed circuit boards.

摘要翻译： 布线设计处理方法是通过使用计算机将印刷电路板的自动布线处理中的各种处理的执行顺序设计为自动布线处理处理。 布线设计处理方法包括：在各个印刷电路板中，在存储单元中存储包括关于印刷电路板的各种物理信息的印刷电路板信息; 根据针对每个印刷电路板分析设置，布线进展和布线情况的结果，在针对每个印刷电路板读取存储在存储单元中的印刷电路板信息之后，自动创建自动布线处理过程 的印刷电路板; 并且对于每个印刷电路板，根据在创建时创建的自动布线处理过程执行自动布线处理。

公开(公告)号：US20090125861A1

公开(公告)日：2009-05-14

申请号：US12222229

申请日：2008-08-05

申请人： Takahiko Orita ,  Eiichi Konno

发明人： Takahiko Orita ,  Eiichi Konno

IPC分类号： G06F17/50

CPC分类号： G06F17/5077

摘要： A wiring design processing method is for designing an automatic wiring processing process as an execution sequence of various processing in automatic wiring processing for printed circuit boards by using a computer. The wiring design processing method includes storing, in a storage unit, printed circuit board information including various physical information regarding the printed circuit boards, for each of the printed circuit boards; creating an automatic wiring processing process automatically according to a result of analyzing setting, wiring progress, and wiring situation at present regarding each of the printed circuit boards, after reading the printed circuit board information, stored in the storage unit at the storing, for each of the printed circuit boards; and executing the automatic wiring processing according to the automatic wiring processing process created at the creating, for each of the printed circuit boards.

摘要翻译： 布线设计处理方法是通过使用计算机将印刷电路板的自动布线处理中的各种处理的执行顺序设计为自动布线处理处理。 布线设计处理方法包括：在各个印刷电路板中，在存储单元中存储包括关于印刷电路板的各种物理信息的印刷电路板信息; 根据针对每个印刷电路板分析设置，布线进展和布线情况的结果，在针对每个印刷电路板读取存储在存储单元中的印刷电路板信息之后，自动创建自动布线处理过程 的印刷电路板; 并且对于每个印刷电路板，根据在创建时创建的自动布线处理过程执行自动布线处理。

公开(公告)号：US20120206460A1

公开(公告)日：2012-08-16

申请号：US13355828

申请日：2012-01-23

申请人： Tomo Kaniwa ,  Takahiko Orita

发明人： Tomo Kaniwa ,  Takahiko Orita

IPC分类号： G06T11/20

CPC分类号： G06T11/203

摘要： A device includes a processor which executes a process including generating data of a second graphic identified by shifting each of first sides of a first graphic by a length in a direction toward an inside of the first graphic and by tracing, in a direction, the first sides after the shifting and intersection points between the first sides after the shifting, generating data of a third graphic by shifting each of second sides of the second graphic to both sides of each of the second side by the length and by linking end points of the second sides after the shifting using a circular arc which is centered on an end point of the second side before the shifting and which has a radius of the length, and generating data of a fourth graphic by performing a logical addition operation between the second graphic and the third graphic.

摘要翻译： 一种设备包括处理器，该处理器包括生成通过将第一图形的第一边的每一个朝向第一图形的内部的方向移动长度而识别的第二图形的数据，并且沿着第一图形的方向 在移动之后的第一边之间的移动和交点之后的两边之间，通过将第二图形的第二边的每一侧移动到第二边的每一边的长度，并且通过将第二图形的端点 在移动之后的第二侧使用在移动之前以第二侧的终点为中心并且具有长度的半径的圆弧，并且通过在第二图形和第二图形之间执行逻辑加法运算来生成第四图形的数据 第三个图形。

公开(公告)号：US08847971B2

公开(公告)日：2014-09-30

申请号：US13355828

申请日：2012-01-23

申请人： Tomo Kaniwa ,  Takahiko Orita

发明人： Tomo Kaniwa ,  Takahiko Orita

IPC分类号： G06T11/20 ,  G09G5/37 ,  G06F17/50

CPC分类号： G06T11/203

摘要： A device includes a processor which executes a process including generating data of a second graphic identified by shifting each of first sides of a first graphic by a length in a direction toward an inside of the first graphic and by tracing, in a direction, the first sides after the shifting and intersection points between the first sides after the shifting, generating data of a third graphic by shifting each of second sides of the second graphic to both sides of each of the second side by the length and by linking end points of the second sides after the shifting using a circular arc which is centered on an end point of the second side before the shifting and which has a radius of the length, and generating data of a fourth graphic by performing a logical addition operation between the second graphic and the third graphic.

摘要翻译： 一种设备包括处理器，该处理器包括生成通过将第一图形的第一边的每一个朝向第一图形的内部的方向移动长度而识别的第二图形的数据，并且沿着第一图形的方向 在移动之后的第一边之间的移动和交点之后的两边之间，通过将第二图形的第二边的每一侧移动到第二边的每一边的长度，并且通过将第二图形的端点 在移动之后的第二侧使用在移动之前以第二侧的终点为中心并且具有长度的半径的圆弧，并且通过在第二图形和第二图形之间执行逻辑加法运算来生成第四图形的数据 第三个图形。

公开(公告)号：US08539432B2

公开(公告)日：2013-09-17

申请号：US13591844

申请日：2012-08-22

申请人： Takahiko Orita

发明人： Takahiko Orita

IPC分类号： G06F17/50

CPC分类号： G06F17/5077

摘要： A computer-readable recording medium stores a program that causes a computer to execute a circuit design process. The process includes selecting component data in first board data from among the first board data including first connector component data and second board data including second connector component data that is associated with the first connector component data; setting a connection destination net name of the selected component data to a first vacant terminal of the first connector component data; and setting the connection destination net name of the component data to a second vacant terminal of the second connector component data that corresponds to the first vacant terminal of the first connector data when the component data is moved from the first board data to the second board data.

摘要翻译： 计算机可读记录介质存储使计算机执行电路设计过程的程序。 该过程包括从包括第一连接器组件数据的第一板数据和包括与第一连接器组件数据相关联的第二连接器组件数据的第二板数据中选择第一板数据中的组件数据; 将所选择的组件数据的连接目的地网络名称设置到所述第一连接器组件数据的第一空闲终端; 以及当所述组件数据从所述第一板数据移动到所述第二板数据时，将所述组件数据的连接目的地网络名称设置为与所述第一连接器数据的所述第一空闲终端对应的所述第二连接器组件数据的第二空闲终端 。