公开(公告)号：US09123441B1

公开(公告)日：2015-09-01

申请号：US14245991

申请日：2014-04-04

Applicant: INPHI CORPORATION

Inventor： David Wang

IPC: G11C5/02 ,  G11C29/00

CPC classification number: G11C29/50016 ,  G11C11/401 ,  G11C29/44

Abstract: A method for testing a memory device. The method can include coupling the memory device to a test apparatus and determining whether each of the memory cells in the memory device is within a first specification range. Each of the cells that fall outside of the first range can be identified. Each of the cells that meet the second specification range can be tested. The method can include selecting a tile associated with a highest number of cells that fall outside of the second range. A resource can then be used to repair each of the cells that fall outside of the second range for a tile associated with a fewer number of cells that fall outside of the second range such that a first number of tiles meets the first range and a second number of tiles meets the second range such that the first number the second number.

Abstract translation: 一种用于测试存储器件的方法。 该方法可以包括将存储器件耦合到测试装置并确定存储器件中的每个存储器单元是否在第一规格范围内。 可以识别落在第一范围之外的每个细胞。 可以测试满足第二规格范围的每个电池。 该方法可以包括选择与第二范围之外的最大数量的单元相关联的瓦片。 然后，可以使用资源来修复落在第二范围之外的每个小区，用于与较少数量的落在第二范围之外的小区相关联的瓦片，使得第一数量的瓦片满足第一范围，并且第二个 瓦数满足第二范围，使第一个数字为第二个数字。

公开(公告)号：US08966327B1

公开(公告)日：2015-02-24

申请号：US13797623

申请日：2013-03-12

Applicant: Inphi Corporation

Inventor： David Wang

IPC: G06F11/07 ,  G06F12/00 ,  G06F11/14

CPC classification number: G06F11/1076 ,  G06F11/008 ,  G06F11/1004 ,  G06F11/1016 ,  G06F12/00

Abstract: A buffer integrated circuit device. The device comprising an output driver formed on the substrate member, the output driver having at least a command bus and an address bus. The device has a protocol and parity checking block (“Block”). The device has a table configured in the block. The table is programmable with a plurality of timing parameters. The device has a memory state block coupled to the table and a command history table coupled to the table to process protocol information for all commands that pass through the Block. The buffer integrated circuit device utilizes the protocol checking functionality to prevent failure propagation and enables data protection even in the case of host memory controller failure or system-level failure of any signal or signals on the command, control and address bus from the host memory controller to the buffer integrated device.

Abstract translation: 缓冲器集成电路器件。 所述装置包括形成在所述衬底构件上的输出驱动器，所述输出驱动器至少具有命令总线和地址总线。 该设备具有协议和奇偶校验块（“块”）。 该设备具有在该块中配置的表。 该表可以用多个定时参数来编程。 该设备具有耦合到该表的存储器状态块和耦合到该表的命令历史表，以处理通过该块的所有命令的协议信息。 缓冲器集成电路器件利用协议检查功能来防止故障传播，并且即使在主机存储器控制器故障或者来自主机存储器控制器的命令，控制和地址总线上的任何信号或信号的系统级故障的情况下也能够进行数据保护 到缓冲器集成器件。