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    Processor hardware and instructions for lattice based cryptography
    13.
    发明授权
    Processor hardware and instructions for lattice based cryptography 有权

    公开(公告)号：US11792005B2

    公开(公告)日：2023-10-17

    申请号：US17699830

    申请日：2022-03-21

    Applicant: Intel Corporation

    Inventor： Santosh Ghosh ,  Andrew H. Reinders ,  Manoj Sastry

    IPC: H04L9/40 ,  H04L9/30

    CPC classification number: H04L9/3093 ,  H04L2209/12

    Abstract: A method comprises fetching, by fetch circuitry, an encoded butterfly instruction comprising an opcode, a first source identifier, a second source identifier, a third source identifier, and two destination identifiers, decoding, by decode circuitry, the decoded butterfly instruction to generate a decoded butterfly instruction, and executing, by execution circuitry, the decoded butterfly instruction to retrieve operands representing a first input polynomial-coefficient from the first source, a second input polynomial-coefficient from the second source, and a primitive nth root of unity from the third source, perform, in an atomic fashion, a butterfly operation to generate a first output polynomial-coefficient and a second output polynomial-coefficient, and store the first output coefficient and the second output coefficient in a register file accessible to the execution circuitry.

    System, Apparatus And Method For Performing A Plurality Of Cryptographic Operations
    15.
    发明申请
    System, Apparatus And Method For Performing A Plurality Of Cryptographic Operations 有权

    公开(公告)号：US20210126786A1

    公开(公告)日：2021-04-29

    申请号：US17144216

    申请日：2021-01-08

    Applicant: Intel Corporation

    Inventor： Santosh Ghosh ,  Andrew H. Reinders ,  Sudhir K. Satpathy ,  Manoj R. Sastry

    IPC: H04L9/30 ,  G06F7/72 ,  G06F7/544 ,  G06F7/00

    Abstract: In one embodiment, an apparatus includes a hardware accelerator to execute cryptography operations including a Rivest Shamir Adleman (RSA) operation and an elliptic curve cryptography (ECC) operation. The hardware accelerator may include a multiplier circuit comprising a parallel combinatorial multiplier, and an ECC circuit coupled to the multiplier circuit to execute the ECC operation. The ECC circuit may compute a prime field multiplication using the multiplier circuit and reduce a result of the prime field multiplication in a plurality of addition and subtraction operations for a first type of prime modulus. The hardware accelerator may execute the RSA operation using the multiplier circuit. Other embodiments are described and claimed.

    PROCESSOR HARDWARE AND INSTRUCTIONS FOR VECTORIZED FUSED AND-XOR
    16.
    发明公开
    PROCESSOR HARDWARE AND INSTRUCTIONS FOR VECTORIZED FUSED AND-XOR 审中-公开

    公开(公告)号：US20230305846A1

    公开(公告)日：2023-09-28

    申请号：US17703194

    申请日：2022-03-24

    Applicant: Intel Corporation

    Inventor： Andrew H. Reinders ,  Santosh Ghosh ,  Manoj Sastry

    IPC: G06F9/30 ,  G06F9/38

    CPC classification number: G06F9/30145 ,  G06F9/30036 ,  G06F9/30029 ,  G06F9/3001 ,  G06F9/3802

    Abstract: A method comprises fetching, by fetch circuitry, an encoded vectorized AND-XOR instruction comprising an opcode, a first source identifier, a second source identifier, a third source identifier, and a destination identifier, decoding, by decode circuitry, the decoded vectorized AND-XOR instruction to generate a decoded vectorized AND-XOR instruction, and executing, by execution circuitry, the decoded vectorized AND-XOR instruction to retrieve operands representing a product coefficient at an index position from the first source, a coefficient of a first polynomial from the second source, and a coefficient of a second polynomial from the third source, perform, in an atomic fashion, a vectorized AND-XOR operation to generate updated value of the product coefficient, and store the product coefficient of the output polynomial in a register file accessible to the execution circuitry.

    POST QUANTUM PUBLIC KEY SIGNATURE OPERATION FOR RECONFIGURABLE CIRCUIT DEVICES
    18.
    发明申请
    POST QUANTUM PUBLIC KEY SIGNATURE OPERATION FOR RECONFIGURABLE CIRCUIT DEVICES 有权

    公开(公告)号：US20220108039A1

    公开(公告)日：2022-04-07

    申请号：US17551961

    申请日：2021-12-15

    Applicant: Intel Corporation

    Inventor： Vikram Suresh ,  Sanu Mathew ,  Rafael Misoczki ,  Santosh Ghosh ,  Raghavan Kumar ,  Manoj Sastry ,  Andrew H. Reinders

    IPC: G06F21/72 ,  G06F21/76 ,  H04L9/32 ,  H04L9/08

    Abstract: Embodiments are directed to post quantum public key signature operation for reconfigurable circuit devices. An embodiment of an apparatus includes one or more processors; and a reconfigurable circuit device, the reconfigurable circuit device including a dedicated cryptographic hash hardware engine, and a reconfigurable fabric including logic elements (LEs), wherein the one or more processors are to configure the reconfigurable circuit device for public key signature operation, including mapping a state machine for public key generation and verification to the reconfigurable fabric, including mapping one or more cryptographic hash engines to the reconfigurable fabric, and combining the dedicated cryptographic hash hardware engine with the one or more mapped cryptographic hash engines for cryptographic signature generation and verification.

    STATE SYNCHRONIZATION FOR POST-QUANTUM SIGNING FACILITIES
    19.
    发明申请
    STATE SYNCHRONIZATION FOR POST-QUANTUM SIGNING FACILITIES 有权

    公开(公告)号：US20220078024A1

    公开(公告)日：2022-03-10

    申请号：US17014600

    申请日：2020-09-08

    Applicant: Intel Corporation

    Inventor： RAFAEL MISOCZKI ,  Andrew H. Reinders ,  Santosh Ghosh ,  Manoj Sastry

    IPC: H04L9/32 ,  H04L9/30 ,  H04L9/06 ,  H04L9/14 ,  H04L9/08 ,  G06N10/00

    Abstract: An apparatus comprises a plurality of hardware security modules, at least a first hardware security module in the plurality of hardware security modules comprising processing circuitry to generate a first plurality of pairs of cryptographic key pairs comprising a first plurality of private keys and a first plurality of public keys, forward the first plurality of public keys to a remote computing device, receive, from the remote computing device, a first plurality of ciphertexts, wherein each ciphertext in the plurality of ciphertexts represents an encryption of a cryptographic seed with a public key selected from the plurality of public keys, receive, from a subset of hardware security modules in the plurality of hardware security modules, a subset of private keys.

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