公开(公告)号：US12093431B2

公开(公告)日：2024-09-17

申请号：US18363176

申请日：2023-08-01

Applicant: Intel Corporation

Inventor： Manoj R. Sastry ,  Alpa Narendra Trivedi ,  Men Long

IPC: G06F21/72 ,  G06F21/85 ,  G09C1/00 ,  H04L9/06 ,  H04L9/08

CPC classification number: G06F21/72 ,  G06F21/85 ,  G09C1/00 ,  H04L9/0643 ,  H04L9/0897 ,  G06F2207/7219 ,  G06F2211/008 ,  G06F2213/0038 ,  H04L2209/76

Abstract: Systems and techniques for a System-on-a-Chip (SoC) security plugin are described herein. A component message may be received at an interconnect endpoint from an SoC component. The interconnect endpoint may pass the component message to a security component via a security interlink. The security component may secure the component message, using a cryptographic engine, to create a secured message. The secured message is delivered back to the interconnect endpoint via the security interlink and transmitted across the interconnect by the interconnect endpoint.

公开(公告)号：US20230284029A1

公开(公告)日：2023-09-07

申请号：US18088442

申请日：2022-12-23

Applicant: Intel Corporation

Inventor： Liuyang Lily Yang ,  Manoj R. Sastry ,  Xiruo Liu ,  Moreno Ambrosin

IPC: H04W12/122 ,  H04W4/40 ,  H04W8/00 ,  G08G1/16 ,  G05D1/00 ,  H04W48/02

CPC classification number: H04W12/122 ,  G05D1/0088 ,  G08G1/164 ,  H04W4/40 ,  H04W8/005 ,  H04W48/02 ,  G05D2201/0213

Abstract: A first roadway system receives a communication from a second roadway system over a wireless channel, where the communication includes a description of a physical object within a driving environment. Characteristics of the physical object are determined based on sensors of the first roadway system. The communication is determined to contain an anomaly based on a comparison of the description of the physical object with the characteristics determined based on the sensors of the first roadway system. Misbehavior data is generated to describe the anomaly. A remedial action is initiated based on the anomaly.

公开(公告)号：US11263352B2

公开(公告)日：2022-03-01

申请号：US16936999

申请日：2020-07-23

Applicant: Intel Corporation

Inventor： Manoj R. Sastry ,  Alpa Narendra Trivedi ,  Men Long

IPC: G06F21/72 ,  G09C1/00 ,  G06F21/85 ,  H04L9/06 ,  H04L9/08

Abstract: Systems and techniques for a System-on-a-Chip (SoC) security plugin are described herein. A component message may be received at an interconnect endpoint from an SoC component. The interconnect endpoint may pass the component message to a security component via a security interlink. The security component may secure the component message, using a cryptographic engine, to create a secured message. The secured message is delivered back to the interconnect endpoint via the security interlink and transmitted across the interconnect by the interconnect endpoint.

公开(公告)号：US20210014806A1

公开(公告)日：2021-01-14

申请号：US17032921

申请日：2020-09-25

Applicant: Intel Corporation

Inventor： Javier Perez-Ramirez ,  Mikhail Galeev ,  Susruth Sudhakaran ,  Dave Cavalcanti ,  Manoj R. Sastry ,  Christopher N. Gutierrez

IPC: H04W56/00 ,  H04L29/06 ,  G06F1/12

Abstract: Systems and methods in which devices synchronize their clocks for purposes of data transmission are described. Particularly, the disclosed systems and methods provide detection and mitigation of interference by malicious (or non-malicious) wireless devices with communication of time synchronized data over wireless networks. Systems and methods are provided where times statistics related to multiple instances of wireless time synchronization are collected and collated. Devices in the system can discipline their internal clocks based on the collated time statistics.

公开(公告)号：US20190327096A1

公开(公告)日：2019-10-24

申请号：US16456058

申请日：2019-06-28

Applicant: Intel Corporation

Inventor： Xiruo Liu ,  Rafael Misoczki ,  Manoj R. Sastry ,  Santosh Ghosh ,  Li Zhao

IPC: H04L9/32 ,  H04L9/06 ,  H04L9/30 ,  H04L9/14

Abstract: An attestation protocol between a prover device (P), a verifier device (V), and a trusted third-party device (TPP). P and TPP have a first trust relationship represented by a first cryptographic representation based on a one-or-few-times, hash-based, signature key. V sends an attestation request to P, with the attestation request including a second cryptographic representation of a second trust relationship between V and TPP. In response to the attestation request, P sends a validation request to TPP, with the validation request being based on a cryptographic association of the first trust relationship and the second trust relationship. TPP provides a validation response including a cryptographic representation of verification of validity of the first trust relationship and the second trust relationship. P sends an attestation response to V based on the validation response.

公开(公告)号：US20190044718A1

公开(公告)日：2019-02-07

申请号：US15982278

申请日：2018-05-17

Applicant: Intel Corporation

Inventor： Santosh Ghosh ,  Andrew H. Reinders ,  Sudhir K. Satpathy ,  Manoj R. Sastry

IPC: H04L9/30 ,  G06F7/72 ,  G06F7/544

Abstract: In one embodiment, an apparatus includes: a hardware accelerator to execute cryptography operations including a Rivest Shamir Adleman (RSA) operation and an elliptic curve cryptography (ECC) operation. The hardware accelerator may include: a multiplier circuit comprising a parallel combinatorial multiplier; and an ECC circuit coupled to the multiplier circuit to execute the ECC operation. The ECC circuit may compute a prime field multiplication using the multiplier circuit and reduce a result of the prime field multiplication in a plurality of addition and subtraction operations for a first type of prime modulus. The hardware accelerator may execute the RSA operation using the multiplier circuit. Other embodiments are described and claimed.

公开(公告)号：US20180337780A1

公开(公告)日：2018-11-22

申请号：US15952720

申请日：2018-04-13

Applicant: Intel Corporation

Inventor： Santosh Ghosh ,  Manoj R. Sastry

IPC: H04L9/30 ,  G09C1/00 ,  H04L9/14 ,  G06F7/72

CPC classification number: H04L9/3066 ,  G06F7/725 ,  G09C1/00 ,  H04L9/14 ,  H04L2209/12 ,  H04L2209/24

Abstract: Embodiments of a system for, and method for using, an elliptic curve cryptography integrated circuit are generally described herein. An elliptic curve cryptography (ECC) operation request may be received. One of a plurality of circuit portions may be instructed to perform the ECC operation. The plurality of circuit portions that may be used include a finite field arithmetic circuit portion, an EC point addition and doubler circuit portion, a finite field exponentiation circuit portion, and a point multiplier circuit portion. The result of the ECC operation may then be output.

公开(公告)号：US20180183574A1

公开(公告)日：2018-06-28

申请号：US15392324

申请日：2016-12-28

Applicant: Intel Corporation

Inventor： Santosh Ghosh ,  Manoj R. Sastry ,  Jesse R. Walker ,  Ravi L. Sahita ,  Abhishek Basak ,  Vedvyas Shanbhogue ,  David M. Durham

IPC: H04L9/06 ,  G06F21/44 ,  G06F21/72

Abstract: Embodiments include a computing processor control flow enforcement system including a processor, a block cipher encryption circuit, and an exclusive-OR (XOR) circuit. The control flow enforcement system uses a block cipher encryption to authenticate a return address when returning from a call or interrupt. The block cipher encryption circuit executes a block cipher encryption on a first number including an identifier to produce a first encrypted result and executes a block cipher encryption on a second number including a return address and a stack location pointer to produce a second encrypted result. The XOR circuit performs an XOR operation on the first encrypted result and the second encrypted result to produce a message authentication code tag.

公开(公告)号：US20170155514A1

公开(公告)日：2017-06-01

申请号：US14955255

申请日：2015-12-01

Applicant: INTEL CORPORATION

Inventor： Steffen Schulz ,  Rafael Misoczki ,  Manoj R. Sastry ,  Jesse Walker

IPC: H04L9/32 ,  H04L9/30 ,  H04L9/14 ,  G06F9/445 ,  H04L29/06

CPC classification number: H04L9/3247 ,  G06F8/65 ,  H04L9/0891 ,  H04L9/14 ,  H04L9/304 ,  H04L9/3242 ,  H04L63/06 ,  H04L63/123 ,  H04L67/34

Abstract: In a method for validating software updates, a data processing system contains a current version of a software component. The data processing system saves at least first and second current advance keys (AKs). After saving the current AKs, the data processing system receives an update package for a new version of the software component. The data processing system extracts a digital signature and two or more new AKs from the update package. The data processing system uses at least one current AK to determine whether the digital signature is valid. In response to a determination that the digital signature is valid, the data processing system uses a software image from the update package to update the software component, and the data processing system saves the new AKs, for subsequent utilization as the current AKs. Other embodiments are described and claimed.

公开(公告)号：US20240179160A1

公开(公告)日：2024-05-30

申请号：US18526456

申请日：2023-12-01

Applicant: Intel Corporation

Inventor： Marcio Rogerio Juliato ,  Shabbir Ahmed ,  Santosh Ghosh ,  Christopher Gutierrez ,  Manoj R. Sastry

IPC: H04L9/40 ,  H04L12/40

CPC classification number: H04L63/1416 ,  H04L12/40 ,  H04L12/40136 ,  H04L63/1466 ,  H04L2012/40215

Abstract: Various systems and methods for bus-off attack detection are described herein. An electronic device for bus-off attack detection and prevention includes bus-off prevention circuitry coupled to a protected node on a bus, the bus-off prevention circuitry to: detect a transmitted message from the protected node to the bus; detect a bit mismatch of the transmitted message on the bus; suspend further transmissions from the protected node while the bus is analyzed; determine whether the bit mismatch represents a bus fault or an active attack against the protected node; and signal the protected node indicating whether a fault has occurred.