公开(公告)号：US11442734B2

公开(公告)日：2022-09-13

申请号：US17216580

申请日：2021-03-29

申请人： Intel Corporation

发明人： Bret L. Toll ,  Buford M. Guy ,  Ronak Singhal ,  Mishali Naik

IPC分类号： G06F9/30

摘要： A processor includes a first mode where the processor is not to use packed data operation masking, and a second mode where the processor is to use packed data operation masking. A decode unit to decode an unmasked packed data instruction for a given packed data operation in the first mode, and to decode a masked packed data instruction for a masked version of the given packed data operation in the second mode. The instructions have a same instruction length. The masked instruction has bit(s) to specify a mask. Execution unit(s) are coupled with the decode unit. The execution unit(s), in response to the decode unit decoding the unmasked instruction in the first mode, to perform the given packed data operation. The execution unit(s), in response to the decode unit decoding the masked instruction in the second mode, to perform the masked version of the given packed data operation.

公开(公告)号：US10228941B2

公开(公告)日：2019-03-12

申请号：US13931047

申请日：2013-06-28

申请人： Intel Corporation

发明人： Bret L. Toll ,  Ronak Singhal ,  Buford M. Guy ,  Mishali Naik

IPC分类号： G06F9/30

摘要： A processor of an aspect includes a set of registers capable of storing packed data. An execution unit is coupled with the set of registers. The execution unit is to access the set of registers in at least two different ways in response to instructions. The at least two different ways include a first way in which the set of registers are to represent a plurality of N-bit registers. The at least two different ways also include a second way in which the set of registers are to represent a single register of at least 2N-bits. In one aspect, the at least 2N-bits is to be at least 256-bits.

公开(公告)号：US09990202B2

公开(公告)日：2018-06-05

申请号：US13931739

申请日：2013-06-28

申请人： Intel Corporation

发明人： Bret L. Toll ,  Ronak Singhal ,  Buford M. Guy ,  Mishali Naik

IPC分类号： G06F9/30

CPC分类号： G06F9/30189 ,  G06F9/30018 ,  G06F9/30036

摘要： A processor includes a first mode where the processor is not to use packed data operation masking, and a second mode where the processor is to use packed data operation masking. A decode unit to decode an unmasked packed data instruction for a given packed data operation in the first mode, and to decode a masked packed data instruction for a masked version of the given packed data operation in the second mode. The instructions have a same instruction length. The masked instruction has bit(s) to specify a mask. Execution unit(s) are coupled with the decode unit. The execution unit(s), in response to the decode unit decoding the unmasked instruction in the first mode, to perform the given packed data operation. The execution unit(s), in response to the decode unit decoding the masked instruction in the second mode, to perform the masked version of the given packed data operation.

公开(公告)号：US09934032B2

公开(公告)日：2018-04-03

申请号：US15331940

申请日：2016-10-24

申请人： Intel Corporation

发明人： Edward T. Grochowski ,  Seyed Yahya Sotoudeh ,  Buford M. Guy

IPC分类号： G06F15/76 ,  G06F15/00 ,  G06F9/30

CPC分类号： G06F9/30036 ,  G06F9/30014 ,  G06F9/30018 ,  G06F9/30032 ,  G06F9/3016

摘要： A method includes receiving a packed data instruction indicating a first narrower source packed data operand and a narrower destination operand. The instruction is mapped to a masked packed data operation indicating a first wider source packed data operand that is wider than and includes the first narrower source operand, and indicating a wider destination operand that is wider than and includes the narrower destination operand. A packed data operation mask is generated that includes a mask element for each corresponding result data element of a packed data result to be stored by the masked packed data operation. All mask elements that correspond to result data elements to be stored by the masked operation that would not be stored by the packed data instruction are masking out. The masked operation is performed using the packed data operation mask. The packed data result is stored in the wider destination operand.

公开(公告)号：US09477467B2

公开(公告)日：2016-10-25

申请号：US13854089

申请日：2013-03-30

申请人： Intel Corporation

发明人： Edward T. Grochowski ,  Seyed Yahya Sotoudeh ,  Buford M. Guy

IPC分类号： G06F15/76 ,  G06F15/00 ,  G06F9/30

CPC分类号： G06F9/30036 ,  G06F9/30014 ,  G06F9/30018 ,  G06F9/30032 ,  G06F9/3016

摘要： A method includes receiving a packed data instruction indicating a first narrower source packed data operand and a narrower destination operand. The instruction is mapped to a masked packed data operation indicating a first wider source packed data operand that is wider than and includes the first narrower source operand, and indicating a wider destination operand that is wider than and includes the narrower destination operand. A packed data operation mask is generated that includes a mask element for each corresponding result data element of a packed data result to be stored by the masked packed data operation. All mask elements that correspond to result data elements to be stored by the masked operation that would not be stored by the packed data instruction are masking out. The masked operation is performed using the packed data operation mask. The packed data result is stored in the wider destination operand.

摘要翻译： 一种方法包括：接收指示第一较窄的源打包数据操作数和较窄的目的地操作数的打包数据指令。 指令被映射到掩码的打包数据操作，指示比第一较窄源操作数宽的第一较宽的源打包数据操作数，并且包括第一较窄的源操作数，并且指示较宽的目的地操作数，并且包括较窄的目的地操作数。 生成打包数据操作掩码，其包括用于通过掩蔽的打包数据操作存储的打包数据结果的每个对应结果数据元素的掩码元素。 对应于由打包数据指令不存储的掩蔽操作存储的结果数据元素的所有掩码元素都将被遮蔽。 使用打包数据操作掩码执行屏蔽操作。 打包数据结果存储在更宽的目标操作数中。