公开(公告)号：US10282296B2

公开(公告)日：2019-05-07

申请号：US15376647

申请日：2016-12-12

申请人： Intel Corporation

发明人： Jason W. Brandt ,  Robert S. Chappell ,  Jesus Corbal ,  Edward T. Grochowski ,  Stephen H. Gunther ,  Buford M. Guy ,  Thomas R. Huff ,  Elmoustapha Ould-Ahmed-Vall ,  Bret L. Toll ,  David Papworth ,  James D. Allen

IPC分类号： G06F12/0831 ,  G06F12/1009 ,  G06F12/1027

摘要： Embodiments of an invention a processor architecture are disclosed. In an embodiment, a processor includes a decoder, an execution unit, a coherent cache, and an interconnect. The decoder is to decode an instruction to zero a cache line. The execution unit is to issue a write command to initiate a cache line sized write of zeros. The coherent cache is to receive the write command, to determine whether there is a hit in the coherent cache and whether a cache coherency protocol state of the hit cache line is a modified state or an exclusive state, to configure a cache line to indicate all zeros, and to issue the write command toward the interconnect. The interconnect is to, responsive to receipt of the write command, issue a snoop to each of a plurality of other coherent caches for which it must be determined if there is a hit.

公开(公告)号：US20220237123A1

公开(公告)日：2022-07-28

申请号：US17712632

申请日：2022-04-04

申请人： Intel Corporation

发明人： Jason W. Brandt ,  Robert S. Chappell ,  Jesus Corbal ,  Edward T. Grochowski ,  Stephen H. Gunther ,  Buford M. Guy ,  Thomas R. Huff ,  Christopher J. Hughes ,  Elmoustapha Ould-Ahmed-Vall ,  Ronak Singhal ,  Seyed Yahya Sotoudeh ,  Bret L. Toll ,  Lihu Rappoport ,  David B. Papworth ,  James D. Allen

IPC分类号： G06F12/0831 ,  G06F12/1027 ,  G06F12/1009 ,  G06F9/30

摘要： Embodiments of an invention a processor architecture are disclosed. In an embodiment, a processor includes a decoder, an execution unit, a coherent cache, and an interconnect. The decoder is to decode an instruction to zero a cache line. The execution unit is to issue a write command to initiate a cache line sized write of zeros. The coherent cache is to receive the write command, to determine whether there is a hit in the coherent cache and whether a cache coherency protocol state of the hit cache line is a modified state or an exclusive state, to configure a cache line to indicate all zeros, and to issue the write command toward the interconnect. The interconnect is to, responsive to receipt of the write command, issue a snoop to each of a plurality of other coherent caches for which it must be determined if there is a hit.

公开(公告)号：US11294809B2

公开(公告)日：2022-04-05

申请号：US16115067

申请日：2018-08-28

申请人： Intel Corporation

发明人： Jason W. Brandt ,  Robert S. Chappell ,  Jesus Corbal ,  Edward T. Grochowski ,  Stephen H. Gunther ,  Buford M. Guy ,  Thomas R. Huff ,  Christopher J. Hughes ,  Elmoustapha Ould-Ahmed-Vall ,  Ronak Singhal ,  Seyed Yahya Sotoudeh ,  Bret L. Toll ,  Lihu Rappoport ,  David Papworth ,  James D. Allen

IPC分类号： G06F12/0831 ,  G06F12/1027 ,  G06F12/1009 ,  G06F9/30

摘要： Embodiments of an invention a processor architecture are disclosed. In an embodiment, a processor includes a decoder, an execution unit, a coherent cache, and an interconnect. The decoder is to decode an instruction to zero a cache line. The execution unit is to issue a write command to initiate a cache line sized write of zeros. The coherent cache is to receive the write command, to determine whether there is a hit in the coherent cache and whether a cache coherency protocol state of the hit cache line is a modified state or an exclusive state, to configure a cache line to indicate all zeros, and to issue the write command toward the interconnect. The interconnect is to, responsive to receipt of the write command, issue a snoop to each of a plurality of other coherent caches for which it must be determined if there is a hit.

公开(公告)号：US10963257B2

公开(公告)日：2021-03-30

申请号：US16586977

申请日：2019-09-28

申请人： Intel Corporation

发明人： Bret L. Toll ,  Buford M. Guy ,  Ronak Singhal ,  Mishali Naik

IPC分类号： G06F9/30

摘要： A processor includes a first mode where the processor is not to use packed data operation masking, and a second mode where the processor is to use packed data operation masking. A decode unit to decode an unmasked packed data instruction for a given packed data operation in the first mode, and to decode a masked packed data instruction for a masked version of the given packed data operation in the second mode. The instructions have a same instruction length. The masked instruction has bit(s) to specify a mask. Execution unit(s) are coupled with the decode unit. The execution unit(s), in response to the decode unit decoding the unmasked instruction in the first mode, to perform the given packed data operation. The execution unit(s), in response to the decode unit decoding the masked instruction in the second mode, to perform the masked version of the given packed data operation.

公开(公告)号：US20150006858A1

公开(公告)日：2015-01-01

申请号：US13931739

申请日：2013-06-28

申请人： Intel Corporation

发明人： BRET L. TOLL ,  Buford M. Guy ,  Ronak Singhal ,  Mishali Nail

IPC分类号： G06F9/30

CPC分类号： G06F9/30189 ,  G06F9/30018 ,  G06F9/30036

摘要： A processor includes a first mode where the processor is not to use packed data operation masking, and a second mode where the processor is to use packed data operation masking. A decode unit to decode an unmasked packed data instruction for a given packed data operation in the first mode, and to decode a masked packed data instruction for a masked version of the given packed data operation in the second mode. The instructions have a same instruction length. The masked instruction has bit(s) to specify a mask. Execution unit(s) are coupled with the decode unit. The execution unit(s), in response to the decode unit decoding the unmasked instruction in the first mode, to perform the given packed data operation. The execution unit(s), in response to the decode unit decoding the masked instruction in the second mode, to perform the masked version of the given packed data operation.

摘要翻译： 处理器包括处理器不使用打包数据操作屏蔽的第一模式，以及处理器将使用打包数据操作屏蔽的第二模式。 解码单元，用于对第一模式中的给定打包数据操作的未屏蔽打包数据指令进行解码，并且解码用于第二模式中给定打包数据操作的屏蔽版本的屏蔽打包数据指令。 指令具有相同的指令长度。 被屏蔽的指令具有指定掩码的位。 执行单元与解码单元耦合。 执行单元响应于解码单元对第一模式中的未屏蔽指令进行解码，以执行给定的打包数据操作。 执行单元响应于解码单元对第二模式中的屏蔽指令进行解码，以执行给定打包数据操作的屏蔽版本。

公开(公告)号：US12130740B2

公开(公告)日：2024-10-29

申请号：US17712632

申请日：2022-04-04

申请人： Intel Corporation

发明人： Jason W. Brandt ,  Robert S. Chappell ,  Jesus Corbal ,  Edward T. Grochowski ,  Stephen H. Gunther ,  Buford M. Guy ,  Thomas R. Huff ,  Christopher J. Hughes ,  Elmoustapha Ould-Ahmed-Vall ,  Ronak Singhal ,  Seyed Yahya Sotoudeh ,  Bret L. Toll ,  Lihu Rappoport ,  David B. Papworth ,  James D. Allen

IPC分类号： G06F12/0831 ,  G06F9/30 ,  G06F9/38 ,  G06F12/1009 ,  G06F12/1027

CPC分类号： G06F12/0831 ,  G06F9/30043 ,  G06F9/384 ,  G06F12/1009 ,  G06F12/1027 ,  G06F2212/1016 ,  G06F2212/621 ,  G06F2212/68

摘要： Embodiments of an invention a processor architecture are disclosed. In an embodiment, a processor includes a decoder, an execution unit, a coherent cache, and an interconnect. The decoder is to decode an instruction to zero a cache line. The execution unit is to issue a write command to initiate a cache line sized write of zeros. The coherent cache is to receive the write command, to determine whether there is a hit in the coherent cache and whether a cache coherency protocol state of the hit cache line is a modified state or an exclusive state, to configure a cache line to indicate all zeros, and to issue the write command toward the interconnect. The interconnect is to, responsive to receipt of the write command, issue a snoop to each of a plurality of other coherent caches for which it must be determined if there is a hit.

公开(公告)号：US10430193B2

公开(公告)日：2019-10-01

申请号：US15995736

申请日：2018-06-01

申请人： Intel Corporation

发明人： Bret L. Toll ,  Buford M. Guy ,  Ronak Singhal ,  Mishali Naik

IPC分类号： G06F9/30

摘要： A processor includes a first mode where the processor is not to use packed data operation masking, and a second mode where the processor is to use packed data operation masking. A decode unit to decode an unmasked packed data instruction for a given packed data operation in the first mode, and to decode a masked packed data instruction for a masked version of the given packed data operation in the second mode. The instructions have a same instruction length. The masked instruction has bit(s) to specify a mask. Execution unit(s) are coupled with the decode unit. The execution unit(s), in response to the decode unit decoding the unmasked instruction in the first mode, to perform the given packed data operation. The execution unit(s), in response to the decode unit decoding the masked instruction in the second mode, to perform the masked version of the given packed data operation.

公开(公告)号：US20190012266A1

公开(公告)日：2019-01-10

申请号：US16115067

申请日：2018-08-28

申请人： Intel Corporation

发明人： Jason W. Brandt ,  Robert S. Chappell ,  Jesus Corbal ,  Edward T. Grochowski ,  Stephen H. Gunther ,  Buford M. Guy ,  Thomas R. Huff ,  Christopher J. Hughes ,  Elmoustapha Ould-Ahmed-Vall ,  Ronak Singhal ,  Seyed Yahya Sotoudeh ,  Bret L. Toll ,  Lihu Rappoport ,  David Papworth ,  James D. Allen

IPC分类号： G06F12/0831 ,  G06F12/1027 ,  G06F12/1009

摘要： Embodiments of an invention a processor architecture are disclosed. In an embodiment, a processor includes a decoder, an execution unit, a coherent cache, and an interconnect. The decoder is to decode an instruction to zero a cache line. The execution unit is to issue a write command to initiate a cache line sized write of zeros. The coherent cache is to receive the write command, to determine whether there is a hit in the coherent cache and whether a cache coherency protocol state of the hit cache line is a modified state or an exclusive state, to configure a cache line to indicate all zeros, and to issue the write command toward the interconnect. The interconnect is to, responsive to receipt of the write command, issue a snoop to each of a plurality of other coherent caches for which it must be determined if there is a hit.

公开(公告)号：US20180165199A1

公开(公告)日：2018-06-14

申请号：US15376647

申请日：2016-12-12

申请人： Intel Corporation

发明人： Jason W. Brandt ,  Robert S. Chappell ,  Jesus Corbal ,  Edward T. Grochowski ,  Stephen H. Gunther ,  Buford M. Guy ,  Thomas R. Huff ,  Christopher J. Hughes ,  Elmoustapha Ould-Ahmed-Vall ,  Ronak Singhal ,  Seyed Yahya Sotoudeh ,  Bret L. Toll ,  Lihu Rappoport ,  David Papworth ,  James D. Allen

IPC分类号： G06F12/0831 ,  G06F12/1027 ,  G06F12/1009

CPC分类号： G06F12/0831 ,  G06F12/1009 ,  G06F12/1027 ,  G06F2212/1016 ,  G06F2212/621 ,  G06F2212/68

摘要： Embodiments of an invention a processor architecture are disclosed. In an embodiment, a processor includes a decoder, an execution unit, a coherent cache, and an interconnect. The decoder is to decode an instruction to zero a cache line. The execution unit is to issue a write command to initiate a cache line sized write of zeros. The coherent cache is to receive the write command, to determine whether there is a hit in the coherent cache and whether a cache coherency protocol state of the hit cache line is a modified state or an exclusive state, to configure a cache line to indicate all zeros, and to issue the write command toward the interconnect. The interconnect is to, responsive to receipt of the write command, issue a snoop to each of a plurality of other coherent caches for which it must be determined if there is a hit.

公开(公告)号：US12039336B2

公开(公告)日：2024-07-16

申请号：US17898418

申请日：2022-08-29

申请人： Intel Corporation

发明人： Bret L. Toll ,  Buford M. Guy ,  Ronak Singhal ,  Mishali Naik

IPC分类号： G06F9/30

CPC分类号： G06F9/30189 ,  G06F9/30018 ,  G06F9/30036

摘要： A processor includes a first mode where the processor is not to use packed data operation masking, and a second mode where the processor is to use packed data operation masking. A decode unit to decode an unmasked packed data instruction for a given packed data operation in the first mode, and to decode a masked packed data instruction for a masked version of the given packed data operation in the second mode. The instructions have a same instruction length. The masked instruction has bit(s) to specify a mask. Execution unit(s) are coupled with the decode unit. The execution unit(s), in response to the decode unit decoding the unmasked instruction in the first mode, to perform the given packed data operation. The execution unit(s), in response to the decode unit decoding the masked instruction in the second mode, to perform the masked version of the given packed data operation.