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公开(公告)号:US09609765B2
公开(公告)日:2017-03-28
申请号:US14129597
申请日:2013-09-27
Applicant: INTEL CORPORATION , Xiaoguo Liang , Chung-Hao Chen , Alexander Uan-Zo-Li , Sheng Ren , Hong W. Wong
Inventor: Xiaoguo Liang , Chung-Hao Chen , Alexander Uan-Zo-Li , Sheng Ren , Hong W. Wong
CPC classification number: H05K5/0026 , G06F1/1613 , G06F1/182 , H01G2/04 , H01G4/30 , H04B15/005 , H04B15/02 , H04M1/0202 , H04M1/0277
Abstract: A chassis for an electronic device may include a first metal layer to form an inner surface of the chassis, an insulating layer on the first metal layer, and a second metal layer on the insulating layer. The second metal layer may be connected to a ground area of a circuit board to be provided in the chassis.
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公开(公告)号:US11189574B2
公开(公告)日:2021-11-30
申请号:US16606628
申请日:2017-05-31
Applicant: Intel Corporation
Inventor: Li-Sheng Weng , Chung-Hao Chen , James C. Matayabas, Jr. , Min Keen Tang
IPC: H01L23/552 , H01L23/31 , H01L23/00 , H05K9/00
Abstract: A microelectronic package may be fabricated with a microelectronic substrate, a microelectronic die electrically attached to the microelectronic substrate, and an electromagnetic interference shield layer contacting one or both of the microelectronic substrate and the microelectronic die, wherein the electromagnetic interference shield layer has an electrical conductivity between about 10,000 siemens per meter and 100,000 siemens per meter. The specific range of electrical conductivity results in electromagnetic fields either generated by the microelectronic die or generated by components external to the microelectronic package scattering within the electromagnetic interference shield layer and attenuating. Thus, the electromagnetic interference shield layer can prevent electromagnetic field interference without the need to be grounded.
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公开(公告)号:US09900976B1
公开(公告)日:2018-02-20
申请号:US15376469
申请日:2016-12-12
Applicant: Intel Corporation
Inventor: Chung-Hao Chen , Min Keen Tang , Li-Sheng Weng
CPC classification number: H05K1/0216 , G06F1/1698 , H05K1/0243 , H05K3/0061
Abstract: Apparatus and method to provide integrated circuit (IC) package integrity without adverse performance degradation are disclosed herein. In some embodiments, an apparatus may include one or more integrated circuits (ICs); a metallic structure that encircles the one or more ICs without being in contact with the one or more ICs, wherein the metallic structure is without an electrical ground; and a conductive epoxy layer disposed below and in contact with the metallic structure, wherein the conductive epoxy is to reduce an electromagnetic field induced by the metallic structure in response to a presence of a wireless signal that operates at approximately a resonant frequency associated with the metallic structure.
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14.
公开(公告)号:US20170289410A1
公开(公告)日:2017-10-05
申请号:US15085926
申请日:2016-03-30
Applicant: Intel Corporation
Inventor: Mohd Muhaiyiddin Bin Abdullah , Chee Kit Chew , Chung-Hao Chen
Abstract: Techniques and mechanisms for exchanging image data via a three-wire data channel of an interconnect, at least a portion of which is disposed in or on a substrate of a printed circuit board. In an embodiment, three data signals are concurrently exchanged in parallel, each via a different respective trace portion of the data channel. The substrate has disposed therein or thereon three filter structures each to perform filtering of a different respective one of the three signals. The filter structures each include a respective sequence of corrugations to increase a stray capacitance provided by a substrate material. In another embodiment, the interconnect is compatible with a Mobile Industry Processor Interface (MIPI) camera physical layer interface (C-PHY) standard.
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公开(公告)号:US20150223351A1
公开(公告)日:2015-08-06
申请号:US14129597
申请日:2013-09-27
Applicant: INTEL CORPORATION
Inventor: Xiaoguo Liang , Chung-Hao Chen , Alexander Uan-Zo-Li , Sheng Ren , Hong W. Wong
CPC classification number: H05K5/0026 , G06F1/1613 , G06F1/182 , H01G2/04 , H01G4/30 , H04B15/005 , H04B15/02 , H04M1/0202 , H04M1/0277
Abstract: A chassis for an electronic device may include a first metal layer to form an inner surface of the chassis, an insulating layer on the first metal layer, and a second metal layer on the insulating layer. The second metal layer may be connected to a ground area of a circuit board to be provided in the chassis.
Abstract translation: 用于电子设备的底架可以包括形成底盘内表面的第一金属层,第一金属层上的绝缘层和绝缘层上的第二金属层。 第二金属层可以连接到要设置在底盘中的电路板的接地区域。
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