公开(公告)号：US11189574B2

公开(公告)日：2021-11-30

申请号：US16606628

申请日：2017-05-31

Applicant: Intel Corporation

Inventor： Li-Sheng Weng ,  Chung-Hao Chen ,  James C. Matayabas, Jr. ,  Min Keen Tang

IPC: H01L23/552 ,  H01L23/31 ,  H01L23/00 ,  H05K9/00

Abstract: A microelectronic package may be fabricated with a microelectronic substrate, a microelectronic die electrically attached to the microelectronic substrate, and an electromagnetic interference shield layer contacting one or both of the microelectronic substrate and the microelectronic die, wherein the electromagnetic interference shield layer has an electrical conductivity between about 10,000 siemens per meter and 100,000 siemens per meter. The specific range of electrical conductivity results in electromagnetic fields either generated by the microelectronic die or generated by components external to the microelectronic package scattering within the electromagnetic interference shield layer and attenuating. Thus, the electromagnetic interference shield layer can prevent electromagnetic field interference without the need to be grounded.

公开(公告)号：US10586779B2

公开(公告)日：2020-03-10

申请号：US15792569

申请日：2017-10-24

Applicant: Intel Corporation

Inventor： Nachiket R. Raravikar ,  James C. Matayabas, Jr. ,  Akshay Mathkar

IPC: H01L25/00 ,  H01L25/10 ,  H01L23/00 ,  H01L23/498 ,  H01L23/538 ,  B23K35/22 ,  B23K35/26 ,  B23K35/36 ,  B23K35/30 ,  B23K35/02 ,  B23K101/40

Abstract: Embodiments describe high aspect ratio and fine pitch interconnects for a semiconductor package, such as a package-on-package structure. In an embodiment, the interconnects are formed with a no-slump solder paste. In an embodiment, the no-slump solder paste is printed in an uncured state, and is then cured with a liquid phase sintering process. After being cured, the no-slump solder paste will not reflow at typical processing temperatures, such as those below approximately 400° C. According to embodiments, the no-slump solder paste includes Cu particles or spheres, a solder matrix component, a polymeric delivery vehicle, and a solvent. In an embodiment, the liquid phase sintering produces a shell of intermetallic compounds around the Cu spheres. In an embodiment, the sintering process builds a conductive metallic network through the no-slump solder paste.

公开(公告)号：US09831206B2

公开(公告)日：2017-11-28

申请号：US14229785

申请日：2014-03-28

Applicant: INTEL CORPORATION

Inventor： Nachiket R. Raravikar ,  James C. Matayabas, Jr. ,  Akshay Mathkar

IPC: H01L23/488 ,  H01L23/00 ,  H01L25/10 ,  H01L23/498 ,  H01L23/532 ,  B23K35/22 ,  H01L23/538 ,  H01L25/00

CPC classification number: H01L24/17 ,  B23K35/22 ,  H01L23/49811 ,  H01L23/5389 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/81815 ,  H01L2224/92125 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/1533 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012

Abstract: Embodiments describe high aspect ratio and fine pitch interconnects for a semiconductor package, such as a package-on-package structure. In an embodiment, the interconnects are formed with a no-slump solder paste. In an embodiment, the no-slump solder paste is printed in an uncured state, and is then cured with a liquid phase sintering process. After being cured, the no-slump solder paste will not reflow at typical processing temperatures, such as those below approximately 400° C. According to embodiments, the no-slump solder paste includes Cu particles or spheres, a solder matrix component, a polymeric delivery vehicle, and a solvent. In an embodiment, the liquid phase sintering produces a shell of intermetallic compounds around the Cu spheres. In an embodiment, the sintering process builds a conductive metallic network through the no-slump solder paste.

公开(公告)号：US09820384B2

公开(公告)日：2017-11-14

申请号：US14102676

申请日：2013-12-11

Applicant: Intel Corporation

Inventor： Sasha Oster ,  Robert L. Sankman ,  Charles Gealer ,  Omkar Karhade ,  John S. Guzek ,  Ravi V. Mahajan ,  James C. Matayabas, Jr. ,  Johanna Swan ,  Feras Eid ,  Shawna Liff ,  Timothy McIntosh ,  Telesphor Kamgaing ,  Adel Elsherbini ,  Kemal Aygun

IPC: H05K1/18 ,  H05K13/04 ,  H01L23/00 ,  H05K1/03 ,  G06F1/16 ,  H01L21/56

CPC classification number: H05K1/189 ,  G06F1/163 ,  H01L21/568 ,  H01L24/19 ,  H01L24/96 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/24137 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/18162 ,  H05K1/0393 ,  H05K1/181 ,  H05K1/185 ,  H05K13/0469 ,  H05K2201/0137 ,  H05K2203/1469 ,  Y10T29/49146 ,  H01L2924/00

Abstract: This disclosure relates generally to devices, systems, and methods for making a flexible microelectronic assembly. In an example, a polymer is molded over a microelectronic component, the polymer mold assuming a substantially rigid state following the molding. A routing layer is formed with respect to the microelectronic component and the polymer mold, the routing layer including traces electrically coupled to the microelectronic component. An input is applied to the polymer mold, the polymer mold transitioning from the substantially rigid state to a substantially flexible state upon application of the input.

公开(公告)号：US11881440B2

公开(公告)日：2024-01-23

申请号：US16798118

申请日：2020-02-21

Applicant: INTEL CORPORATION

Inventor： Marely E. Tejeda Ferrari ,  Taylor Gaines ,  Elah Bozorg-Grayeli ,  James C. Matayabas, Jr.

IPC: H01L23/373 ,  H01L21/48 ,  H01L23/367 ,  H01L23/42 ,  C08K3/04 ,  C09K5/14

CPC classification number: H01L23/3737 ,  C08K3/041 ,  C08K3/042 ,  C09K5/14 ,  H01L21/4871 ,  H01L23/367 ,  H01L23/42 ,  C08K2201/001 ,  C08K2201/011

Abstract: Microelectronic devices, assemblies, and systems include a microelectronic die and composite material to conduct heat from the microelectronic die such that the composite material includes polymer chains chemically bonded to fill particles having a hexagonal lattice of carbon atoms such as graphene sheet fill particles and/or carbon nanotube fill particles.

公开(公告)号：US11545407B2

公开(公告)日：2023-01-03

申请号：US16244748

申请日：2019-01-10

Applicant: Intel Corporation

Inventor： Kumar Abhishek Singh ,  Omkar Karhade ,  Nitin Deshpande ,  Mitul Modi ,  Edvin Cetegen ,  Aastha Uppal ,  Debendra Mallik ,  Sanka Ganesan ,  Yiqun Bai ,  Jan Krajniak ,  Manish Dubey ,  Ravindranath Mahajan ,  Ram Viswanath ,  James C. Matayabas, Jr.

IPC: H01L23/10 ,  H01L23/34 ,  H01L23/31 ,  H01L23/00 ,  H01L23/48 ,  H01L21/56 ,  H01L21/48

Abstract: An integrated circuit package may be formed having at least one heat dissipation structure within the integrated circuit package itself. In one embodiment, the integrated circuit package may include a substrate; at least one integrated circuit device, wherein the at least one integrated circuit device is electrically attached to the substrate; a mold material on the substrate and adjacent to the at least one integrated circuit device; and at least one heat dissipation structure contacting the at least one integrated circuit, wherein the at least one heat dissipation structure is embedded either within the mold material or between the mold material and the substrate.

公开(公告)号：US12046536B2

公开(公告)日：2024-07-23

申请号：US16398452

申请日：2019-04-30

Applicant: Intel Corporation

Inventor： Je-Young Chang ,  James C. Matayabas, Jr. ,  Zhimin Wan ,  Kyle Arrington

IPC: H01L23/473 ,  H01L23/367 ,  H01L23/373 ,  H05K7/20

CPC classification number: H01L23/473 ,  H01L23/367 ,  H01L23/3733 ,  H05K7/20309 ,  H05K7/20327 ,  H05K7/20336

Abstract: An integrated circuit package includes a first die and second die above a substrate, and a vapor chamber above at least one of the first and second die. A vapor space within the vapor chamber is separated into at least a first section and a second section. The first section may be over the first die, and the second section may be over the second die, for example. The structure separating the first and second sections at least partly restricts flow of vapor between the first and second sections, thereby preventing or reducing thermal cross talk between the first and second dies. In some cases, an anisotropic thermal material is above one of the first or second die, wherein the anisotropic thermal material has substantially higher thermal conductivity in a direction of a heat sink than a thermal conductivity in a direction of a section of the vapor chamber.

公开(公告)号：US11562940B2

公开(公告)日：2023-01-24

申请号：US16296898

申请日：2019-03-08

Applicant: Intel Corporation

Inventor： Elizabeth Nofen ,  James C. Matayabas, Jr. ,  Yawei Liang ,  Yiqun Bai

IPC: H01L23/00 ,  H01L23/373 ,  H01L23/367 ,  F28F21/08 ,  H01L21/48

Abstract: An apparatus is provided which comprises: a die comprising an integrated circuit, a first material layer comprising a first metal, the first material layer on a surface of the die, and extending at least between opposite lateral sides of the die, a second material layer comprising a second metal over the first material layer, and a third material layer comprising silver particles and having a porosity greater than that of the second material layer, the third material layer between the first material layer and the second material layer. Other embodiments are also disclosed and claimed.

公开(公告)号：US20210118809A1

公开(公告)日：2021-04-22

申请号：US16606628

申请日：2017-05-31

Applicant: Intel Corporation

Inventor： Li-Sheng Weng ,  Chung-Hao Chen ,  James C. Matayabas, Jr. ,  Min Keen Tang

IPC: H01L23/552 ,  H01L23/31 ,  H05K9/00 ,  H01L23/00

Abstract: A microelectronic package may be fabricated with a microelectronic substrate, a microelectronic die electrically attached to the microelectronic substrate, and an electromagnetic interference shield layer contacting one or both of the microelectronic substrate and the microelectronic die, wherein the electromagnetic interference shield layer has an electrical conductivity between about 10,000 siemens per meter and 100,000 siemens per meter. The specific range of electrical conductivity results in electromagnetic fields either generated by the microelectronic die or generated by components external to the microelectronic package scattering within the electromagnetic interference shield layer and attenuating. Thus, the electromagnetic interference shield layer can prevent electromagnetic field interference without the need to be grounded.

公开(公告)号：US10056314B2

公开(公告)日：2018-08-21

申请号：US14736120

申请日：2015-06-10

Applicant: INTEL CORPORATION

Inventor： Randall D. Lowe, Jr. ,  Syadwad Jain ,  James C. Matayabas, Jr.

IPC: H01L23/373 ,  C08L83/04 ,  C09C3/12 ,  H01L23/367 ,  H01L23/42 ,  B32B5/16 ,  C08K3/22 ,  C08K3/08 ,  C08K3/28

CPC classification number: H01L23/3737 ,  B32B5/16 ,  C08K2003/0806 ,  C08K2003/0812 ,  C08K2003/085 ,  C08K2003/2227 ,  C08K2003/2296 ,  C08K2003/282 ,  C08L83/04 ,  C09C3/12 ,  H01L23/3672 ,  H01L23/3675 ,  H01L23/3736 ,  H01L23/42 ,  H01L2224/16225 ,  H01L2224/73253 ,  H01L2924/15311 ,  H01L2924/16152 ,  C08K3/28 ,  C08K3/10

Abstract: A polymer thermal interface material is described that has enhanced thermal conductivity. In one example, a vinyl-terminated silicone oil is combined with a silicone chain extender, and a thermally conductive filler comprising at least 85% by weight of the material, and comprising surface wetted particles with a range of shapes and sizes. The material may be used for bonding components inside a microelectronic package, for example.