公开(公告)号：US20210094179A1

公开(公告)日：2021-04-01

申请号：US16955388

申请日：2018-03-29

Applicant: Intel Corporation

Inventor： Ganmei You ,  Dawei Wang ,  Ling Liu ,  Xuesong Shi ,  Chunjie Wang

IPC: B25J9/16 ,  G06F16/901 ,  G06F9/22

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to improve resource utilization for binary tree structures. An example apparatus to improve resource utilization for field programmable gate array (FPGA) resources includes a computation determiner to identify a computation capability value associated with the FPGA resources, a k-ary tree builder to build a first k-ary tree having a number of k-ary nodes equal to the computation capability value, and an FPGA memory controller to initiate collision computation by transferring the first k-ary tree to a first memory of the FPGA resources.