公开(公告)号：US20240028907A1

公开(公告)日：2024-01-25

申请号：US16649523

申请日：2017-12-28

Applicant: Intel Corporation

Inventor： Xuesong Shi ,  Zhigang Wang

IPC: G06N3/094 ,  G06N3/0475

CPC classification number: G06N3/094 ,  G06N3/0475

Abstract: Training data generators and methods for machine learning are disclosed. An example method to generate training data for machine learning by generating simulated training data for a target neural network, transforming, with a training data transformer, the simulated training data form transformed training data, the training data transformer trained to increase a conformance of the transformed training data and the simulated training data, and training the target neural network with the transformed training data.

公开(公告)号：US20220057232A1

公开(公告)日：2022-02-24

申请号：US17299722

申请日：2018-12-12

Applicant: Intel Corporation

Inventor： Yingzhe Shen ,  Zhigang Wang ,  Xuesong Shi

IPC: G01C21/00 ,  G01C21/32

Abstract: A time-aware occupancy mapping using regression to unknown (“RTU”) analysis, and an apparatus to dynamically allocate occupancy probability to a cell in an environment to thereby form a time-aware occupancy map of the environment are disclosed. The apparatus includes a memory circuitry in communication with a processor circuitry, the memory circuitry configured to receive and store probability information from the processor circuitry and to store the probability value and its corresponding time stamp at a probability table. The processor circuitry may be configured to, among others: (1) receive occupancy information, the occupancy information defining whether a first of a plurality of cells (102, 104, 106 and 108) in the environment is occupied; (2) determine a first probability value that the first cell is occupied at a first point in time; (3) direct the first probability value and its corresponding timestamp to the memory circuitry to store; (4) determine a second probability value that the first cell is occupied at a second point in time, the second point in time defined by a lapsed interval from the first point in time to the second point in time; and (5) update the memory circuitry to store the second probability value and its corresponding timestamp.

公开(公告)号：US20240257374A1

公开(公告)日：2024-08-01

申请号：US18565791

申请日：2021-09-23

Applicant: Intel Corporation

Inventor： Xuesong Shi ,  Sangeeta Manepalli ,  Rita Chattopadhyay ,  Peng Wang ,  Yimin Zhang

IPC: G06T7/579 ,  G06T7/73

CPC classification number: G06T7/579 ,  G06T7/73 ,  G06T2207/20081 ,  G06T2207/20084

Abstract: An apparatus to facilitate learning reliable keypoints in situ with introspective self-supervision is disclosed. The apparatus includes one or more processors to provide a view-overlapped keyframe pair from a pose graph that is generated by a visual simultaneous localization and mapping (VSLAM) process executed by the one or more processors: determine a keypoint match from the view-overlapped key frame pair based on a keypoint detection and matching process, the keypoint match corresponding to a keypoint: calculate an inverse reliability score based on matched pixels corresponding to the keypoint match in the view-overlapped keyframe pair: identify a supervision signal associated with the keypoint match, the supervision signal comprising a keypoint reliability score of the keypoint based on a final pose output of the VSLAM process; and train a keypoint detection neural network using the keypoint match, the inverse reliability score, and the keypoint reliability score.

公开(公告)号：US11534917B2

公开(公告)日：2022-12-27

申请号：US16955388

申请日：2018-03-29

Applicant: Intel Corporation

Inventor： Ganmei You ,  Dawei Wang ,  Ling Liu ,  Xuesong Shi ,  Chunjie Wang

IPC: G06F9/46 ,  B25J9/16 ,  G06F9/30 ,  G06V10/94 ,  G06F9/48 ,  G06F9/50

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to improve resource utilization for binary tree structures. An example apparatus to improve resource utilization for field programmable gate array (FPGA) resources includes a computation determiner to identify a computation capability value associated with the FPGA resources, a k-ary tree builder to build a first k-ary tree having a number of k-ary nodes equal to the computation capability value, and an FPGA memory controller to initiate collision computation by transferring the first k-ary tree to a first memory of the FPGA resources.

公开(公告)号：US11829119B2

公开(公告)日：2023-11-28

申请号：US17256199

申请日：2018-12-12

Applicant: Intel Corporation

Inventor： Dawei Wang ,  Ling Liu ,  Xuesong Shi ,  Chunjie Wang ,  Ganmei You

IPC: B25J9/16 ,  B60W50/06 ,  G05B19/4155

CPC classification number: G05B19/4155 ,  B25J9/1666 ,  B60W50/06 ,  G05B2219/32386 ,  G05B2219/34024 ,  G05B2219/50391 ,  G06T2210/12 ,  G06T2210/21

Abstract: Methods and apparatus relating to FPGA (Field-Programmable Gate Array) based acceleration in robot motion planning are described. In an embodiment, logic circuitry (such as an FPGA), coupled to a processor, accelerates one or more motion planning operations for a plurality of objects. A first memory, coupled to the logic circuitry, stores data corresponding to a plurality of Oriented Bounding Boxes (OBBs). The plurality of OBBs are to provide Bounding Volume (BV) models for the plurality of objects. Other embodiments are also disclosed and claimed.

公开(公告)号：US11599751B2

公开(公告)日：2023-03-07

申请号：US16649049

申请日：2017-12-28

Applicant: Intel Corporation

Inventor： Zhigang Wang ,  Xuesong Shi

IPC: G06K9/62 ,  G06F30/20 ,  G06N3/08 ,  G06V10/46

Abstract: Methods, apparatus, systems, and articles of manufacture to simulate sensor data are disclosed. An example apparatus includes a noise characteristic identifier to extract a noise characteristic associated with a feature present in first sensor data obtained by a physical sensor. A feature identifier is to identify a feature present in second sensor data. The second sensor data is generated by an environment simulator simulating a virtual representation of the real sensor. A noise simulator is to synthesize noise-adjusted simulated sensor data based on the feature identified in the second sensor data and the noise characteristic associated with the feature present in the first sensor data.

公开(公告)号：US20210263501A1

公开(公告)日：2021-08-26

申请号：US17256199

申请日：2018-12-12

Applicant: Intel Corporation

Inventor： Dawei Wang ,  Ling Liu ,  Xuesong Shi ,  Chunjie Wang ,  Ganmei You

IPC: G05B19/4155 ,  B25J9/16

Abstract: Methods and apparatus relating to FPGA (Field-Programmable Gate Array) based acceleration in robot motion planning are described. In an embodiment, logic circuitry (such as an FPGA), coupled to a processor, accelerates one or more motion planning operations for a plurality of objects. A first memory, coupled to the logic circuitry, stores data corresponding to a plurality of Oriented Bounding Boxes (OBBs). The plurality of OBBs are to provide Bounding Volume (BV) models for the plurality of objects. Other embodiments are also disclosed and claimed.

公开(公告)号：US11650058B2

公开(公告)日：2023-05-16

申请号：US16633976

申请日：2017-08-28

Applicant: Intel Corporation

Inventor： Xuesong Shi

IPC: G01S17/00 ,  G01C21/20 ,  G01S7/48 ,  G01S17/42 ,  G01S17/89

CPC classification number: G01C21/20 ,  G01S7/4808 ,  G01S17/42 ,  G01S17/89

Abstract: Apparatus for determining a current pose of a mobile autonomous apparatus is presented. In embodiments, an apparatus may include interface circuitry to receive detection and ranging data outputted by a Light Detection and Ranging (LIDAR) sensor that nominally sweeps and provides D degrees of detection and ranging data in continuous plurality of quanta, each covering a portion of the D degrees sweep, every time period T. The apparatus may further include pose estimation circuitry coupled to the interface circuitry to determine and provide a current pose of the mobile autonomous apparatus every fractional time period t, independent of when the LIDAR sensor actually completes each sweep. In embodiments, the apparatus may be disposed on the mobile autonomous apparatus.

公开(公告)号：US20210094179A1

公开(公告)日：2021-04-01

申请号：US16955388

申请日：2018-03-29

Applicant: Intel Corporation

Inventor： Ganmei You ,  Dawei Wang ,  Ling Liu ,  Xuesong Shi ,  Chunjie Wang

IPC: B25J9/16 ,  G06F16/901 ,  G06F9/22

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to improve resource utilization for binary tree structures. An example apparatus to improve resource utilization for field programmable gate array (FPGA) resources includes a computation determiner to identify a computation capability value associated with the FPGA resources, a k-ary tree builder to build a first k-ary tree having a number of k-ary nodes equal to the computation capability value, and an FPGA memory controller to initiate collision computation by transferring the first k-ary tree to a first memory of the FPGA resources.

公开(公告)号：US20200218941A1

公开(公告)日：2020-07-09

申请号：US16649049

申请日：2017-12-28

Applicant: Intel Corporation

Inventor： Zhigang Wang ,  Xuesong Shi

IPC: G06K9/62 ,  G06N3/08 ,  G06K9/48 ,  G06F30/20

Abstract: Methods, apparatus, systems, and articles of manufacture to simulate sensor data are disclosed. An example apparatus includes a noise characteristic identifier to extract a noise characteristic associated with a feature present in first sensor data obtained by a physical sensor. A feature identifier is to identify a feature present in second sensor data. The second sensor data is generated by an environment simulator simulating a virtual representation of the real sensor. A noise simulator is to synthesize noise-adjusted simulated sensor data based on the feature identified in the second sensor data and the noise characteristic associated with the feature present in the first sensor data.