公开(公告)号：US20210094179A1

公开(公告)日：2021-04-01

申请号：US16955388

申请日：2018-03-29

Applicant: Intel Corporation

Inventor： Ganmei You ,  Dawei Wang ,  Ling Liu ,  Xuesong Shi ,  Chunjie Wang

IPC: B25J9/16 ,  G06F16/901 ,  G06F9/22

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to improve resource utilization for binary tree structures. An example apparatus to improve resource utilization for field programmable gate array (FPGA) resources includes a computation determiner to identify a computation capability value associated with the FPGA resources, a k-ary tree builder to build a first k-ary tree having a number of k-ary nodes equal to the computation capability value, and an FPGA memory controller to initiate collision computation by transferring the first k-ary tree to a first memory of the FPGA resources.

公开(公告)号：US11829119B2

公开(公告)日：2023-11-28

申请号：US17256199

申请日：2018-12-12

Applicant: Intel Corporation

Inventor： Dawei Wang ,  Ling Liu ,  Xuesong Shi ,  Chunjie Wang ,  Ganmei You

IPC: B25J9/16 ,  B60W50/06 ,  G05B19/4155

CPC classification number: G05B19/4155 ,  B25J9/1666 ,  B60W50/06 ,  G05B2219/32386 ,  G05B2219/34024 ,  G05B2219/50391 ,  G06T2210/12 ,  G06T2210/21

Abstract: Methods and apparatus relating to FPGA (Field-Programmable Gate Array) based acceleration in robot motion planning are described. In an embodiment, logic circuitry (such as an FPGA), coupled to a processor, accelerates one or more motion planning operations for a plurality of objects. A first memory, coupled to the logic circuitry, stores data corresponding to a plurality of Oriented Bounding Boxes (OBBs). The plurality of OBBs are to provide Bounding Volume (BV) models for the plurality of objects. Other embodiments are also disclosed and claimed.

公开(公告)号：US20210263501A1

公开(公告)日：2021-08-26

申请号：US17256199

申请日：2018-12-12

Applicant: Intel Corporation

Inventor： Dawei Wang ,  Ling Liu ,  Xuesong Shi ,  Chunjie Wang ,  Ganmei You

IPC: G05B19/4155 ,  B25J9/16

Abstract: Methods and apparatus relating to FPGA (Field-Programmable Gate Array) based acceleration in robot motion planning are described. In an embodiment, logic circuitry (such as an FPGA), coupled to a processor, accelerates one or more motion planning operations for a plurality of objects. A first memory, coupled to the logic circuitry, stores data corresponding to a plurality of Oriented Bounding Boxes (OBBs). The plurality of OBBs are to provide Bounding Volume (BV) models for the plurality of objects. Other embodiments are also disclosed and claimed.

公开(公告)号：US11534917B2

公开(公告)日：2022-12-27

申请号：US16955388

申请日：2018-03-29

Applicant: Intel Corporation

Inventor： Ganmei You ,  Dawei Wang ,  Ling Liu ,  Xuesong Shi ,  Chunjie Wang

IPC: G06F9/46 ,  B25J9/16 ,  G06F9/30 ,  G06V10/94 ,  G06F9/48 ,  G06F9/50

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to improve resource utilization for binary tree structures. An example apparatus to improve resource utilization for field programmable gate array (FPGA) resources includes a computation determiner to identify a computation capability value associated with the FPGA resources, a k-ary tree builder to build a first k-ary tree having a number of k-ary nodes equal to the computation capability value, and an FPGA memory controller to initiate collision computation by transferring the first k-ary tree to a first memory of the FPGA resources.