公开(公告)号：US20220077055A1

公开(公告)日：2022-03-10

申请号：US17524665

申请日：2021-11-11

Applicant: Intel Corporation

Inventor： Smita SHRIDHARAN ,  Zheng GUO ,  Eric A. KARL ,  George SHCHUPAK ,  Tali KOSINOVSKY

IPC: H01L23/528 ,  H01L23/535 ,  H01L27/092 ,  H01L27/11

Abstract: Memory bit cells having internal node jumpers are described. In an example, an integrated circuit structure includes a memory bit cell on a substrate. The memory bit cell includes first and second gate lines parallel along a second direction of the substrate. The first and second gate lines have a first pitch along a first direction of the substrate, the first direction perpendicular to the second direction. First, second and third interconnect lines are over the first and second gate lines. The first, second and third interconnect lines are parallel along the second direction of the substrate. The first, second and third interconnect lines have a second pitch along the first direction, where the second pitch is less than the first pitch. One of the first, second and third interconnect lines is an internal node jumper for the memory bit cell.

公开(公告)号：US20180219015A1

公开(公告)日：2018-08-02

申请号：US15747414

申请日：2015-09-25

Applicant: Intel Corporation

Inventor： Donald W. NELSON ,  Eric A. KARL

IPC: H01L27/11 ,  G11C11/418 ,  G11C11/419

CPC classification number: H01L27/1104 ,  G11C11/413 ,  G11C11/418 ,  G11C11/419 ,  H01L27/1116

Abstract: Techniques and mechanisms for exchanging signals with one or more transistors at a front side of a semiconductor substrate. In an embodiment, an integrated circuit include a cell—such as a static random access memory (SRAM) cell—comprising transistor structures variously disposed in or on a first side of a substrate. After fabrication of such transistor structures, substrate material may be thinned to expose a second side of the substrate, opposite the first side. A first interconnect and a second interconnect are coupled each to exchange a signal or a voltage. In another embodiment, respective portions of the first interconnect and the second interconnect extend on opposite sides of the substrate, wherein the first side and the second side each extend between such interconnect portions. Positioning of interconnect structures on opposite sides of the substrate allow for performance improvements due to low interconnect resistances.