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    POWER GATE WITH METAL ON BOTH SIDES
    1.
    发明申请
    POWER GATE WITH METAL ON BOTH SIDES 审中-公开

    公开(公告)号：US20200066854A1

    公开(公告)日：2020-02-27

    申请号：US15746799

    申请日：2015-09-25

    申请人： Intel Corporation

    发明人： Donald W. NELSON

    IPC分类号： H01L29/417 ,  H01L29/78 ,  H01L29/66 ,  H01L27/088

    摘要： An apparatus including a circuit structure including a device stratum including a plurality of transistor devices each including a first side defined by a gate electrode and an opposite second side; and a gated supply grid disposed on the second side of the structure, wherein a drain of the at least one of the plurality of transistor devices is coupled to the gated supply grid. A method including providing a supply from a package substrate to power gate transistors in a device layer of a circuit structure, the transistors coupled to circuitry operable to receive a gated supply from the power gate transistors; and distributing the gated supply from the power gate transistors to the circuitry using a grid on an underside of the device layer.

    DYNAMIC LOGIC BUILT WITH STACKED TRANSISTORS SHARING A COMMON GATE
    2.
    发明申请
    DYNAMIC LOGIC BUILT WITH STACKED TRANSISTORS SHARING A COMMON GATE 审中-公开

    公开(公告)号：US20190355756A1

    公开(公告)日：2019-11-21

    申请号：US15774556

    申请日：2015-12-26

    申请人： Intel Corporation

    发明人： Donald W. NELSON ,  Rishabh MEHANDRU

    IPC分类号： H01L27/12 ,  H01L21/822 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/06

    摘要： A dynamic logic circuit including a first transistor within a first device stratum of a substrate; and a second transistor within a second device stratum of the substrate that is different from the first device stratum, wherein the first transistor and the second transistor share a common gate electrode. A method including disposing a second semiconductor body of a second transistor on a first semiconductor body of a first transistor in a first device stratum on a substrate, the second semiconductor body defining a second device stratum; and forming a common gate electrode on each of the semiconductor body and the second semiconductor body.

    ARCHITECTURE TO COMMUNICATE SIGNALS FOR OPERATING A STATIC RANDOM ACCESS MEMORY
    5.
    发明申请
    ARCHITECTURE TO COMMUNICATE SIGNALS FOR OPERATING A STATIC RANDOM ACCESS MEMORY 审中-公开

    公开(公告)号：US20180219015A1

    公开(公告)日：2018-08-02

    申请号：US15747414

    申请日：2015-09-25

    申请人： Intel Corporation

    发明人： Donald W. NELSON ,  Eric A. KARL

    IPC分类号： H01L27/11 ,  G11C11/418 ,  G11C11/419

    CPC分类号： H01L27/1104 ,  G11C11/413 ,  G11C11/418 ,  G11C11/419 ,  H01L27/1116

    摘要： Techniques and mechanisms for exchanging signals with one or more transistors at a front side of a semiconductor substrate. In an embodiment, an integrated circuit include a cell—such as a static random access memory (SRAM) cell—comprising transistor structures variously disposed in or on a first side of a substrate. After fabrication of such transistor structures, substrate material may be thinned to expose a second side of the substrate, opposite the first side. A first interconnect and a second interconnect are coupled each to exchange a signal or a voltage. In another embodiment, respective portions of the first interconnect and the second interconnect extend on opposite sides of the substrate, wherein the first side and the second side each extend between such interconnect portions. Positioning of interconnect structures on opposite sides of the substrate allow for performance improvements due to low interconnect resistances.

    UNIDIRECTIONAL METAL ON LAYER WITH EBEAM
    6.
    发明申请
    UNIDIRECTIONAL METAL ON LAYER WITH EBEAM 审中-公开
    带EBEAM的单层金属

    公开(公告)号：US20170077029A1

    公开(公告)日：2017-03-16

    申请号：US15122396

    申请日：2014-12-19

    申请人： Intel Corporation

    发明人： Donald W. NELSON ,  Yan A. BORODOVSKY ,  Mark C. PHILLIPS

    IPC分类号： H01L23/528 ,  H01L27/11 ,  H01L21/768 ,  H01L27/02

    CPC分类号： H01L23/5283 ,  H01J37/045 ,  H01J37/3177 ,  H01J2237/0435 ,  H01J2237/0453 ,  H01J2237/303 ,  H01J2237/30422 ,  H01J2237/30438 ,  H01J2237/31762 ,  H01J2237/31764 ,  H01L21/0277 ,  H01L21/31144 ,  H01L21/76816 ,  H01L21/76886 ,  H01L27/0207 ,  H01L27/11

    摘要： Lithographic apparatuses suitable for, and methodologies involving, complementary e-beam lithography (CEBL) are described. In an example, a layout for a metallization layer of an integrated circuit includes a first region having a plurality of unidirectional lines of a first width and a first pitch and parallel with a first direction. The layout also includes a second region having a plurality of unidirectional lines of a second width and a second pitch and parallel with the first direction, the second width and the second pitch different than the first width and the first pitch, respectively. The layout also includes a third region having a plurality of unidirectional lines of a third width and a third pitch and parallel with the first direction, the third width and the third pitch different than the first and second widths and different than the first and second pitches.

    摘要翻译： 描述适用于涉及补充电子束光刻（CEBL）的光刻设备和方法。 在一个示例中，集成电路的金属化层的布局包括具有第一宽度和第一间距的多个单向线并与第一方向平行的第一区域。 布局还包括具有第二宽度和第二间距的多个单向线并且与第一方向平行的第二区域，第二宽度和第二间距分别与第一宽度和第一间距不同的第二区域。 布局还包括具有第三宽度和第三间距的多个单向线并且与第一方向平行的第三区域，第三宽度和第三间距不同于第一和第二宽度并且不同于第一和第二间距 。

    EBEAM ALIGN ON THE FLY
    7.
    发明申请
    EBEAM ALIGN ON THE FLY 审中-公开
    飞行中的EBEAM对齐

    公开(公告)号：US20170076967A1

    公开(公告)日：2017-03-16

    申请号：US15122792

    申请日：2014-12-22

    申请人： Intel Corporation

    发明人： Yan A. BORODOVSKY ,  Donald W. NELSON ,  Mark C. PHILLIPS

    IPC分类号： H01L21/68

    CPC分类号： H01L21/682 ,  H01J37/045 ,  H01J37/3026 ,  H01J37/3177 ,  H01J2237/0435 ,  H01J2237/0453 ,  H01J2237/24578 ,  H01J2237/30438 ,  H01J2237/31762 ,  H01J2237/31764 ,  H01L21/0277 ,  H01L21/31144

    摘要： Lithographic apparatuses suitable for, and methodologies involving, complementary e-beam lithography (CEBL) are described. In an example, a method of real-time alignment of a wafer situated on a stage of an e-beam tool involves collecting backscattered electrons from an underlying patterned feature of the wafer while an e-beam column of the e-beam tool writes during scanning of the stage. The collecting is performed by an electron detector placed at the e-beam column bottom. The method also involves performing linear corrections of an alignment of the stage relative to the e-beam column based on the collecting.

    摘要翻译： 描述适用于涉及补充电子束光刻（CEBL）的光刻设备和方法。 在一个示例中，位于电子束工具的台上的晶片的实时对准的方法涉及从电子束工具的电子束列的电子束列中收集来自晶片的底层图案化特征的反向散射电子， 扫描舞台。 收集由放置在电子束柱底部的电子检测器进行。 该方法还涉及基于收集来执行阶段相对于电子束列的对准的线性校正。

    METAL ON BOTH SIDES WITH CLOCK GATED-POWER AND SIGNAL ROUTING UNDERNEATH
    8.
    发明申请
    METAL ON BOTH SIDES WITH CLOCK GATED-POWER AND SIGNAL ROUTING UNDERNEATH 审中-公开

    公开(公告)号：US20190122985A1

    公开(公告)日：2019-04-25

    申请号：US16227406

    申请日：2018-12-20

    申请人： Intel Corporation

    发明人： Donald W. NELSON ,  Patrick MORROW ,  Kimin JUN

    IPC分类号： H01L23/528 ,  H01L23/00 ,  H01L21/768

    摘要： A method including forming a plurality of first interconnects and a plurality of second interconnects on opposite sides of an integrated circuit device layer including a plurality of circuit devices, wherein the plurality of second interconnects include interconnects of different dimensions; and forming contact points to the second plurality of interconnects, the contact points operable for connection to an external source. An apparatus including a substrate including a plurality of first interconnects and a plurality of second interconnects on opposite sides of an integrated circuit device layer including a plurality of circuit devices, wherein the plurality of second interconnects include interconnects of different dimensions; and contact points coupled to the second plurality of interconnects, the contact points operable for connection to an external source.

    METAL ON BOTH SIDES WITH POWER DISTRIBUTED THROUGH THE SILICON
    9.
    发明申请
    METAL ON BOTH SIDES WITH POWER DISTRIBUTED THROUGH THE SILICON 审中-公开

    公开(公告)号：US20180218973A1

    公开(公告)日：2018-08-02

    申请号：US15747988

    申请日：2015-09-25

    申请人： Intel Corporation

    发明人： Donald W. NELSON ,  Mark T. BOHR ,  Patrick MORROW

    IPC分类号： H01L23/498 ,  H01L23/528 ,  H01L49/02

    CPC分类号： H01L23/49827 ,  H01L23/5286 ,  H01L28/00 ,  H01L2224/16227

    摘要： An apparatus including a circuit structure including a device stratum; and a contact coupled to a supply line and routed through the device stratum and coupled to at least one device on a first side. A method including providing a supply from a package substrate to at least one transistor in a device stratum of a circuit structure; and distributing the supply to the at least one transistor using a supply line on an underside of the device stratum and contacting the at least one transistor on a device side by routing a contact from the supply line through the device stratum. A system including a package substrate, and a die including at least one supply line disposed on an underside of a device stratum and routed through the device stratum and coupled to at least one of a plurality of transistor devices on the device side.