UNIFORM LAYOUTS FOR SRAM AND REGISTER FILE BIT CELLS

    公开(公告)号:US20200058656A1

    公开(公告)日:2020-02-20

    申请号:US16605903

    申请日:2017-06-22

    Abstract: Uniform layouts for SRAM and register file bit cells are described. In an example, an integrated circuit structure includes a six transistor (6T) static random access memory (SRAM) bit cell on a substrate. The 6T SRAM bit cell includes first and second active regions parallel along a first direction of the substrate. First, second, third and fourth gate lines are over the first and second active regions, the first, second, third and fourth gate lines parallel along a second direction of the substrate, the second direction perpendicular to the first direction.

    APPARATUS FOR ADAPTIVE WRITE ASSIST FOR MEMORY
    3.
    发明申请
    APPARATUS FOR ADAPTIVE WRITE ASSIST FOR MEMORY 审中-公开
    适用于记忆的自适应写入辅助装置

    公开(公告)号:US20170011793A1

    公开(公告)日:2017-01-12

    申请号:US15115464

    申请日:2014-03-05

    CPC classification number: G11C11/419 G11C7/04 G11C7/22 G11C29/021 G11C29/028

    Abstract: Described is an apparatus which comprises: a memory; a first power supply node to receive a first power supply; a second power supply node coupled to the memory to provide the memory with second power supply; a circuit coupled to the first and second power supply nodes, the circuit operable to dynamically modulate droop in the second power supply by adaptively adjusting signal characteristics of a write assist pulse.

    Abstract translation: 描述了一种装置,包括:存储器; 第一电源节点,用于接收第一电源; 耦合到所述存储器以向所述存储器提供第二电源的第二电源节点; 耦合到所述第一和第二电源节点的电路,所述电路可操作以通过自适应地调整写入辅助脉冲的信号特性来动态地调制所述第二电源中的下降。

    INTERNAL NODE JUMPER FOR MEMORY BIT CELLS
    5.
    发明申请

    公开(公告)号:US20200098682A1

    公开(公告)日:2020-03-26

    申请号:US16604807

    申请日:2017-06-20

    Abstract: Memory bit cells having internal node jumpers are described. In an example, an integrated circuit structure includes a memory bit cell on a substrate. The memory bit cell includes first and second gate lines parallel along a second direction of the substrate. The first and second gate lines have a first pitch along a first direction of the substrate, the first direction perpendicular to the second direction. First, second and third interconnect lines are over the first and second gate lines. The first, second and third interconnect lines are parallel along the second direction of the substrate. The first, second and third interconnect lines have a second pitch along the first direction, where the second pitch is less than the first pitch. One of the first, second and third interconnect lines is an internal node jumper for the memory bit cell.

    INTERNAL NODE JUMPER FOR MEMORY BIT CELLS
    6.
    发明公开

    公开(公告)号:US20230223339A1

    公开(公告)日:2023-07-13

    申请号:US18119225

    申请日:2023-03-08

    CPC classification number: H01L23/528 H01L23/535 H10B10/12 H01L27/0924

    Abstract: Memory bit cells having internal node jumpers are described. In an example, an integrated circuit structure includes a memory bit cell on a substrate. The memory bit cell includes first and second gate lines parallel along a second direction of the substrate. The first and second gate lines have a first pitch along a first direction of the substrate, the first direction perpendicular to the second direction. First, second and third interconnect lines are over the first and second gate lines. The first, second and third interconnect lines are parallel along the second direction of the substrate. The first, second and third interconnect lines have a second pitch along the first direction, where the second pitch is less than the first pitch. One of the first, second and third interconnect lines is an internal node jumper for the memory bit cell.

    INTERNAL NODE JUMPER FOR MEMORY BIT CELLS

    公开(公告)号:US20250125259A1

    公开(公告)日:2025-04-17

    申请号:US18999916

    申请日:2024-12-23

    Abstract: Memory bit cells having internal node jumpers are described. In an example, an integrated circuit structure includes a memory bit cell on a substrate. The memory bit cell includes first and second gate lines parallel along a second direction of the substrate. The first and second gate lines have a first pitch along a first direction of the substrate, the first direction perpendicular to the second direction. First, second and third interconnect lines are over the first and second gate lines. The first, second and third interconnect lines are parallel along the second direction of the substrate. The first, second and third interconnect lines have a second pitch along the first direction, where the second pitch is less than the first pitch. One of the first, second and third interconnect lines is an internal node jumper for the memory bit cell.

    UNIFORM LAYOUTS FOR SRAM AND REGISTER FILE BIT CELLS

    公开(公告)号:US20250071963A1

    公开(公告)日:2025-02-27

    申请号:US18946106

    申请日:2024-11-13

    Abstract: Uniform layouts for SRAM and register file bit cells are described. In an example, an integrated circuit structure includes a six transistor (6T) static random access memory (SRAM) bit cell on a substrate. The 6T SRAM bit cell includes first and second active regions parallel along a first direction of the substrate. First, second, third and fourth gate lines are over the first and second active regions, the first, second, third and fourth gate lines parallel along a second direction of the substrate, the second direction perpendicular to the first direction.

    INTERNAL NODE JUMPER FOR MEMORY BIT CELLS
    9.
    发明公开

    公开(公告)号:US20240213154A1

    公开(公告)日:2024-06-27

    申请号:US18599049

    申请日:2024-03-07

    CPC classification number: H01L23/528 H01L23/535 H01L27/0924 H10B10/12

    Abstract: Memory bit cells having internal node jumpers are described. In an example, an integrated circuit structure includes a memory bit cell on a substrate. The memory bit cell includes first and second gate lines parallel along a second direction of the substrate. The first and second gate lines have a first pitch along a first direction of the substrate, the first direction perpendicular to the second direction. First, second and third interconnect lines are over the first and second gate lines. The first, second and third interconnect lines are parallel along the second direction of the substrate. The first, second and third interconnect lines have a second pitch along the first direction, where the second pitch is less than the first pitch. One of the first, second and third interconnect lines is an internal node jumper for the memory bit cell.

    CHANNEL DEPOPULATION FOR FORKSHEET TRANSISTORS

    公开(公告)号:US20240164080A1

    公开(公告)日:2024-05-16

    申请号:US18375858

    申请日:2023-10-02

    CPC classification number: H10B10/12 H01L29/0669 H01L29/1037

    Abstract: Embodiments disclosed herein include forksheet transistor devices with depopulated channels. In an example, an integrated circuit structure includes a backbone. A first transistor device includes a first vertical stack of semiconductor channels adjacent to a first edge of the backbone. The first vertical stack of semiconductor channels includes first semiconductor channels and a second semiconductor channel over or beneath the first semiconductor channels. A concentration of a dopant in the first semiconductor channels is less than a concentration of the dopant in the second semiconductor channel. A second transistor device includes a second vertical stack of semiconductor channels adjacent to a second edge of the backbone opposite the first edge.

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