公开(公告)号：US10784274B1

公开(公告)日：2020-09-22

申请号：US16441500

申请日：2019-06-14

Applicant: Intel Corporation

Inventor： Rahul Agarwal ,  Srivardhan Gowda ,  Krishna Parat

IPC: H01L27/1157 ,  H01L27/11556 ,  H01L27/11524 ,  H01L23/532 ,  H01L27/11582

Abstract: An integrated circuit memory cell includes a floating gate, a control gate, and a plurality of inter-poly dielectric (IPD) layers. The IPD layers include an IPD1 layer, an IPD2 layer, and an IPD3 layer, with the IPD2 layer interposed between the IPD1 and IPD3 layers. The IPD2 layer, which may be a nitride, does not flank the floating gate. Thus, no section of the floating gate is laterally between two sections of the IPD2 layer. Also, no section of the IPD2 layer of a first memory cell is between the floating gate of the first memory cell and a floating gate of an immediate adjacent memory cell of the same memory cell string. In some cases, an IPD4 layer is provided between the floating gate and the IPD3 layer. The IPD4 layer is relatively much thinner than layers IPD1-3 and may flank the floating gate, as may the IPD3 layer.

公开(公告)号：US20200152793A1

公开(公告)日：2020-05-14

申请号：US16190135

申请日：2018-11-13

Applicant: Intel Corporation

Inventor： Prashant Majhi ,  Khaled Hasnat ,  Krishna Parat

IPC: H01L29/78 ,  H01L27/11524 ,  H01L27/11556 ,  H01L21/28 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/16 ,  H01L29/04

Abstract: A memory structure can include a conductive channel, a charge storage structure adjacent to the conductive channel, and a strain-inducing layer adjacent to the conductive channel on a side opposite the charge storage structure. The strain-inducing layer can have a higher coefficient of thermal expansion (CTE) than the conductive channel.