公开(公告)号：US20210313991A1

公开(公告)日：2021-10-07

申请号：US17350577

申请日：2021-06-17

Applicant: Intel Corporation

Inventor： Archanna Srinivasan ,  Ravi Gutala ,  Scott Weber ,  Aravind Dasu ,  Mahesh Iyer ,  Eriko Nurvitadhi

IPC: H03K19/17788 ,  H03K19/17792 ,  H03K19/17728

Abstract: A circuit system includes a first integrated circuit die having a first group of circuits configured to perform a first set of operations. The circuit system also includes a second integrated circuit die having a second group of circuits configured to start performing a second set of operations with a delay after the first group of circuits starts performing the first set of operations to reduce power supply voltage droop. The operations performed by the first and second groups of circuits can be interleaved with a fixed or a variable delay. Logic circuits can be partitioned into the first and the second groups of circuits based on predicted switching activity of the logic circuits. Decoupling capacitors in integrated circuit dies can be coupled together to reduce droop in a supply voltage during a high current event.